Hi,
In a Virtex II pro design operating at 250 MHz, the FPGA interfaces to an ADC, does some preliminary signal processing, and transmits data to a DSP upon having filled a local buffer with data. The FPGA is the lowest speed grade in the family and I've been tasked with making the design works no matter what. Our data with is 10 bits.
Part of a detection criteria, samples have to be screened before being admitted to further processing. This involves making sure that data is above certain threshold. Now, right in the middle of the dynamic range of the sample width, when I subtract the threshold value from that sample, a momentary glitch appear on the tenth bit making it impossible to tell whether the difference is positive or negative. Because the sampled data corresponds to physical entity that is naturally limited in bandwidth, this transition of sign occurs rather smoothly. Thus I managed to butcher my way through by omitting thresholding on this very case in which a reversal of sign occurs. The caveat obviously is not logging this particular transition sample.
So though the design works for now, I was wondering whether there exists a more elegant/clever solution around this.
Many thanks,
-Mani