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V4 and DDR2 666

Hi all,

Xilinx has announced support for DDR2 up to 533 MHz. Are there any physical limitations that won't allow higher frequencies to be used?

-Fernando

Reply to
fortiz80
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Umm.. That's 533M*bit* (267MHz).

You could try: a) Working through the app notes (I know at least some of them have timing budget calculations) b) Attempting to build a simple design using something like the memory interface generator, and targeting it to a specific chip.

These might provide you with more information.. My guess would be that losing 350 ps odd off the timing budget would be the killer - the question of why could probably be answered by examining it in the above fashion.

I'd be curious myself actually - particularly if you ran through these and came to the conclusion that it could be done...

Jeremy

Reply to
Jeremy Stringer

Jeremy,

I saw a photo of a demo pcb from Japan with an LX60 which has 333MHz DDR RAM chips on it. I was looking at it for the power disctribution system performance, not the DDR interface.

It looked very nice.

If interested, please email directly, and I can give you the contact. That is all I know.

Aust> snipped-for-privacy@gmail.com wrote:

Reply to
Austin Lesea

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