Using very large number in VHDL

Howdy Nick (although this reply would help mikelinyoho/frankgerlach22 as well),

The quality of the answers you get in comp.arch.fpga are usually proportional to the amount of detailed information included in the question.

In your case, you have provided only two (mostly insignificant) pieces of info: you have a single largish number and you want to do something to it that might or might not involve some carry bits.

To get a good answer, you'll need to explain what you are trying to do, and if possible, why you are trying to do it. There are lots of very sharp people in this newsgroup, and for open-ended questions like these, they often identify solutions that the OP never even considered.

In short, when asking a question in this newsgroup, you need to include as much detail as possible:

1. What's the 10,000 foot (high-level) view of what you're trying to do?
2. What are the details (low-level view) of what you're trying to do?
3. What solution(s) have you already identified?

1. What function(s) surround this one?

1. What's the interface to the surrounding functions (speed/width/protocol)?

1. Which vendor/part number/speed grade are you trying to use?

1. What clock speed(s) are being fed to the FPGA pins?
2. Is there a limit to the amount of time it can take to perform the function?

Have fun,

Marc

And efficiently

Use signed or unsigned types and functions from the numeric_std library and a synchronous process.

Try a simple synthesis try first and check static timing for Fmax.

-- Mike Treseler

Sorry about the lack of details :)

I need to compute an adress in a RAM given the following parameter : page group, page number and offset (so typically it's PG*page_size*number_pages + page_number*page_size + offset) The size of the page is 833 850. A group of page contains 16 pages, and there are up to 1024 pages.

This computation does not work simply using Quartus (the output is too large)

Then I split this adress in two, take the most significants bits to adress the RAM (in 8*64 bits) and the 9 less significants bits to adress in the data block (take one bit from the 8*64)

The speed is not really an issue. The design works at 50 MHz, but I could use several clocks ticks to do this (actually I already use 4 for smaller size), but I could go to up to 20 without drawback.

The design is supposed to work on a Cyclone EP1C20, speed grade 7

The solution I identified would be use megafunctions allowing more than 32 bits for the operands so I could do my computation and split without problem. But then I concerned with portability of the design

A later solution would be to compress the data so the size of the page is smaller (at least 2 times) but it wouldn't be enough to come under the 32 bits limit.

Thanks Nick

See if you can use simple concatenation instead of most of your computations...

/Mikhail

Howdy Nick,

In case you didn't understand what Mikhail is suggesting, concatenation for this type of thing would look something like this:

address(34 downto ) > Sorry about the lack of details :)

I did understand what he said, but if I do this I'll waste most of the space in ram (833 850 isn't nicely divided by 2 ...)

Nick