Using the 7 segment displays on Xilinx Spartan 3 kit

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I am trying to understand the working of the multiplexed seven seg.
displays on the xilinx spartan 3 board.the manual does not give me
detailed info. I am trying to write a simple program where I switch a
switch to the on position and it should display "0012" on the displays.
Any suggestions please?

thanks


Re: Using the 7 segment displays on Xilinx Spartan 3 kit
Hi.

Here's some code that I used to display digits/letters on the 7-seg
displays:

module set_7seg_displays (
    // *** Inputs ***
    input    wire        clk_50mhz,      // System clock. (50 MHz)
        input   wire            btn,    // Button 0. (Active High).

        // *** Outputs ***
        output    reg    [3:0]    digit,// 7-seg display enables. (Active Low).
        output    reg    [7:0]    seg  // 7-Segment display. (Active Low).

        );

// 7-Segment display. seg[7:0]={ca, cb, cc, cd, ce, cf, cg, dp}.
wire            rst_n;          // System Reset. (Active Low).
reg     [25:0]  slow_cnt_h;
reg             slow_clk_2h;
reg             slow_clk_h;
reg     [1:0]   cd;

// Assign reset to a button push.
assign rst_n = ~btn;

// *** Create a 2x 7-Seg display clock ***
always @(posedge clk_50mhz or negedge rst_n)
begin : CLK_GEN_2x_7SEG
        if (!rst_n)
        begin
                slow_clk_2h <= 1'b0;
                slow_cnt_h <= 26'b0;
        end
        else
        begin
                if (slow_cnt_h == 26'h001_86A0)
                begin
                        slow_clk_2h <= 1'b1;
                        slow_cnt_h <= 26'h0;
                end
                else
                begin
                        slow_clk_2h <= 1'b0;
                        slow_cnt_h <= slow_cnt_h + 1'b1;
                end
        end
end

// *** Create 1x 7-Seg Display clock ***
always @(posedge slow_clk_2h or negedge rst_n)
begin : CLK_GEN_1x_7SEG
        if (!rst_n)
                slow_clk_h <= 1'b0;
        else
                slow_clk_h <= ~slow_clk_h;
end

// *** Drive the 7-segment display ***
always @(posedge slow_clk_h or negedge rst_n)
begin : SET_7SEGDISPLAY
        if (!rst_n)
        begin
            seg <= 8'hFF;
        digit <= 4'hF;
            cd <= 2'b00;
        end
        else
        begin
              // Cycle through all 4 7-segment displays.
              // Rolls over from 3 to 0. cnt sequence: 0,1,2,3,0,1,2,3
            cd[1:0] <= cd[1:0] + 1'b1 ;
            case (cd[1:0])
                    2'b00 : begin
                             seg <= 8'b0001_0001; // Letter: A (0x11)
                             digit <= 4'b0111;
                            end
                    2'b01 : begin
                             seg <= 8'b0100_1001; // Letter: S (0x49)
                             digit <= 4'b1011;
                            end
                    2'b10 : begin
                             seg <= 8'b0001_0001; // Letter: A (0x11)
                             digit <= 4'b1101;
                            end
                    2'b11 : begin
                             seg <= 8'b0011_0001; // Letter: P (0x31)
                             digit <= 4'b1110;
                            end
                  default : begin
                             seg <= 8'b0000_0010; // Number: 0 (0x02)
                             digit <= 4'b0111;
                            end
                endcase
        end
end

NOTE:  This code keeps the digits/letters continuously lit.

Hope this helps,

Jeremy

fpgawizz wrote:
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displays.


Re: Using the 7 segment displays on Xilinx Spartan 3 kit
Hi Jeremy,

since this _is_ tutorial stuff, I must point out that clocking from
derived logic is a very very bad idea.  I'm sure you must have ignored
tools warnings to get this to compile.

FPGAs have dedicated paths for the clocking lines separate from logic ..
and the twine shall never meet.  There are so many reasons why this is a
bad idea, but basically the tools have to contrain timing quite
intensely to get this working at all and you might just have been lucky.

The correct way to derive a new clock is using a DLL, DCM, PLL, what
have you.  In this simple case however, there's another simple fix you
could use: Just calculate which cycle of the fast clock is safe to use.

...
wire [26:0] slow_cnt;
wire slow_ce = slow_cnt == 2*'h001_86A0;
always @(posedge clk_50MHz) begin
   slow_cnt <= slow_ce ? 0 : slow_cnt+1;
   if (slow_ce) begin
     cd <= cd + 1;
     case (cd)
     'b00 : begin
       seg <= 'b0001_0001; // Letter: A (0x11)
etc..

Tommy


snipped-for-privacy@ieee.org wrote:
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Re: Using the 7 segment displays on Xilinx Spartan 3 kit
Grief, pre-coffee post.  Should know better.  Slight better code:

reg [26:0] slow_cnt;
always @(posedge clk_50MHz)
   if (slow_cnt)
     slow_cnt <= slow_cnt - 1;
   else begin // 50MHz / 20kHz = 2.5 kHz
     slow_cnt <= 200000;
     cd <= cd + 1;
     case (cd)
     'b00 : begin
       seg <= 'b0001_0001; // Letter: A (0x11)
etc..

Re: Using the 7 segment displays on Xilinx Spartan 3 kit
Hi Tommy,

As far as synthesis or p & r warnings for the code I provided above, I
can't recall seeing any. This wasn't a timing critical design, and the
code was mainly used to get a quick and dirty measurement of the
required clock speed to keep the 7-segment displays lit while
multiplexing between the 4 displays.  And it was also used to test the
multiplexing scheme for the displays.

Thanks for the info,

Jeremy


Re: Using the 7 segment displays on Xilinx Spartan 3 kit

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I think everyone who gets the starter kit must end up writing their own
driver for the 7 segment display.

Shame there isn't a bit more simple 'IP' provided with the kit.

Apart from the Xilinx examples I didn't find much in the way of resources
for the starter kit on the web.

Would there be interest in a Yahoo group or something to share Spartan 3
starter kit related files?




Re: Using the 7 segment displays on Xilinx Spartan 3 kit
Yes. I would be interested in a usergroup for xilinx spartan 3 kit users.


Re: Using the 7 segment displays on Xilinx Spartan 3 kit

Hi,

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Please check out http://www.engr.sjsu.edu/crabill for a set
of labs/experiments you can try with the Spartan-3 Starter
kit...  I have tried to touch on most of the resources with
the exception of the SRAM.

// opinion_on

This kit is well named, a "starter" kit.  If everything is
simply handed to you, you don't learn anything.  That's why
it makes such a great educational tool.

If a time multiplexed seven-segment display is challenging
enough for someone to make an appeal to this newsgroup, they
should go through the exercise of designing it themselves.
Maybe with a little help...  We are all learners, just at
different places on the path.  I think to include resources
like this with the kit itself (or posted to this newsgroup)
defeats its utility as a learning tool.

// opinion_off

Good luck!
Eric

Re: Using the 7 segment displays on Xilinx Spartan 3 kit

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Thanks for the pointer.

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I didn't buy the kit to learn FPGA basics, I bought it as a cheap
development platform.

I spent about 3 hours pawing through the documentation to write a top level
verilog module and matching constraints file which defined all the I/O on
the board and expansion connectors. I didn't learn anything it was just
tedious and error prone. The only thing I discovered (learnt) writing a hex
display module for the 7 segment LEDs was that the anodes have inverting
drivers.

I wrote the hex display module to use as a diagnostic tool.

That is the kind of basic 'IP' which I was disappointed not to find in the
box.

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But would enhance its utility as a development platform.


Re: Using the 7 segment displays on Xilinx Spartan 3 kit
The example 'Digital Clock using Multiplexed 7-Segment Display' has VHDL
code on how to do the multiplexed seven segment display.

The example can be downloaded from:
http://www.xilinx.com/s3boards

Cheers,
Shalin-



fpgawizz wrote:
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