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System Ace: How many FPGA's in the JTAG chain before require buffers?

I am designing a board with 9 Xilinx V4FX60 FPGA's configured via System Ace CF controller.

Does anyone have any experience regarding the max number of FPGA's in a JTAG chain that can be succesfully configured?

Was any signal buffering required to acieve this?

Thanks

Jason

Reply to
jason.stubbs
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9 is a big number. Be very careful of the clocks. I wouldn't expect problems with anything else. 
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Reply to
Hal Murray

Jason,

The Rosetta arrays use 100 devices in a single chain.

We do buffer the clock to groups of ten FPGAs at a time.

Aust> I am designing a board with 9 Xilinx V4FX60 FPGA's configured via

Reply to
Austin Lesea

in a

I just got a JTAG analysis done on my board. Interestingly, they strongly suggested buffering TMS as well as TCK.

Marc

Reply to
Marc Randolph

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