We have a board with 15 Altera FPGAs and 12 Configuration circuits (9xEPC2 and 3xEPC8). In the JTAG chain one FPGA (1K100484) sometimes falsifies the data stream. It pushes the data stream by one bit - but always for a length of appr. 8 bits, thenafter the stream recovers. Thus it is hard to program the Configuration chips. It is still possible for the EPC2s, sometimes two or three approaches are needed. Practically impossible for the EPC8s due to their longer programming process. The error even shows when we read out ID. The stream looks like:20 10 00 DD 01 00 20 DD 10 08 00 6E 81 00 20 DD 01 00 A0 DD
When we bridge over the JTAG data lines of this single FPGA the error disappears. The FPGA has no longer or different JTAG I/O lines than the other FPGAs in the board. Is this a frequent error?
Janos Ero CERN Div. EP