Hi All,
I'm interested in how a D flip flop can be made such that the Set and Reset signals can be configured as either synchronous or asynchronous.
Does anyone have any ideas how Xilinx implement their async/sync CLB flip flops?
Do they use asynchronous flips flops with a wrapper of logic so that the set and reset signals can be 'made' synchronous? (The only solution I've come up with so far).
Or is there some lower level flip-flop design that allows a switch between sync and async set and reset?
BTW, this is for an ASIC implementation, rather than an FPGA design.
Anyone any ideas? Thanks Andy