Hi Folks,
in my ALTERA based cpld design (no on-chip pll) i need to low-jitter phase lock a frequency of 6.144 Mhz to a second frequency of 10 MHz. The greatest common divisor of these two numbers is 16000, so i use LPM_COUNTER with modulus 625 to divide the 10 MHz down to 16000 Hz and a modulus 384 LPM_COUNTER to divide the 6.144 MHz to 16000 Hz, everything ok up to this point.
For low-jitter phase comparison usually a xor phase comparator is used. For a xor phase comparator i need the input signals to have an exact 1:1 duty cycle. Since the modulus counters generate only a short (1 clock) impulse when the modulus condition is given, i put a divide-by-two flip-flop behind each counter to produce a 8000 Hz 1:1 duty cycle signal.
While this may work in reality, i get a QUARTUS warning saying that i drive clock inputs with gate outputs. This is clearly true because the modulus output decodes the counter states, but then: What is the "official" way to generate a 1:1 duty cycle signal out of a modulus counter that obeyes the rule that only clocks should feed clock inputs?
TIA for your help Ulrich Bangert