Single Ended signal in sync with V5 GTP

On Aug 5, 4:06 pm, "Eddie H" wrote: [...]

and it does not quite match with 1.5V single ended signal (DDR3 type output) [...]

the start of packet. And after that it needs to stay high.

signal ended signle determines the start of packet.

generate the single ended signal and the GTP output is going to be deterministic from power cycle to power cycle so if I can put a fixed ODELAY on the single ended output then it wlll be synchronous to the GTP output running at 400Mbps. Is that right assumption?

not supported by Xilinx select I/O so I can not use the Select I/O to replace the GTP functionality.

Howdy Eddie,

I don't suppose suggesting the use of a more reasonable protocol would be of much help, would it? :-)

There are FIFO's in the receive and transmit paths of the GTP's. I don't know about the V5's, but V2Pro receive FIFO wasn't completely deterministic on its own, although you could do some things to make the window quite small (within a few clock cycles).

As for interfacing single ended to differential, there are a number of vendors which provide inexpensive popcorn logic to do that.

At first I thought this was for DDR3, but I'm not sure how that fits in with this "start of packet" signal. What protocol is this?

Good luck,

Marc

Marc,

This protocol is defined by one of the university and I need to see if I can use the FPGA to support it. I understand that it is not slam dunk fpga solution but I am trying to make it work. The protocol command consists of 8 bittimes of the ddr clock. The single ended signal needs to lineup with the first bit time to indicate the start of the bit time. The first bittime starts at the deassertion of the single ended signal. The receiver will sample this at the first rising edge of the ddr clock.

Here is a sequence of events:

(1) DDR clock keeps toggling and the single ended signal is asserted. (2) Bit time 0 = single ended signal is sampled deasserted at the rising edge of the ddr clock (3) Bit time 1 = faling edge of ddr clock (4) Bit time 2 = rising edge of ddr clock (5) Bit time 3 = falling edge of ddr clock (6) bit time 4 = rising edge of ddr clock (7) bit time 5 = falling edge of ddr clock (8) bit time 6 = rising edge of ddr clock (9) bit time 7 = falling edge of ddr clock

Then it starts back to bit time0 bit time 0 = rising edge of ddr clock, The GTPs send out meaningful command on this bit time0 window. This command lasts till bit time7 and then again there is bit time0 for idle bus or to generate another command.

The single ended signal gets de-asserted first before the rising edge of the ddr clock in order to signify the bit time0 and then the gtp output can be generated as long as it is bit time0 aligned.

If the fabric clock which generates both the single ended output and feeds the parallel data, has fixed timing relationship with the GTP circuit then this can possibly be achieved by initial board calibration. If the intenal fpga delay is deterministic from power cycle to power cycle then the board calibration will determine the required odelay value to align the single ended output with the bit time0 window.

My main question is - timing relationship between the fabric and the gtp circuit is fixed? If fixed then there is a solution is that correct?

Thanks.

Eddie

Any Ideas?

Why use the GTP at all ? At 400 MBps, an ISERDES based solution should work I think.

Sylvain

400Mbps is the power-up speed but eventually it needs to run at higher speed not supported by the Select I/O.

Is it possible to feed the GTP output from V5 back to the V5 Select I/O differential input? The output will then go in the FPGA fabric and the FPGA will inturn genetrate the single ended 1.5V output. The advantage with this approach is that we are dealing with fixed known delays from power cycle to power cycle.

Question is can the select I/O differential input accept the GTP output which is of CML type. I can not use the GTP receiver as it requires 8b/10b enabled and probably more work. Prefer to use the select I/O.

Eddie