John Lark>> >>
>>> John Lark>>>> This is the thing I'm working on this month. It's a delay generator,
>>>> with an MC68332 uP on the back side that manages things. One of my
>>>> guys quit, leaving behind about 14 klines of nasty, buggy code, so I
>>>> thought it over for about 18 seconds and tossed it and started over
>>>> from scratch. I'm workin with another guy who is re-doing the nasty,
>>>> buggy FPGA design, ditto. He says bad things about the V8.2/SP3 Xilinx
>>>> WebPack software.
>>>>
>>>> The application program is in flash, soldered down, and we're going to
>>>> include a flash boot-block thing that lets you reflash the app code
>>>> through the serial or ethernet ports, to upgrade the firmware. That's
>>>> sort of mind-boggling, since the flash which holds this boot program
>>>> disappears from the uP bus while it's being erased or programmed.
>>>>
>>>> John
>>>>
>>>>
>>>>
>>> That's an interesting non-ortho arrangement :)
>>>
>>> On Webpack 8.2 SP3, I am afraid he's right. There have been some
>>> rumblings on comp.arch.fpga about it recently, and I 'upgraded' to it
>>> for my latest design, and then it would not process 3 previous designs,
>>> although those have no errors I can see. Xilinx claimed it had
>>> 'tightened up' certain things, but it caused me some grief because those
>>> designs are the basis for a number of things where the FPGA code is
>>> designed to in-system upgradeable should some new feature be requested.
>>> I eventually re-installed (from an old full download) 7.1 for those
>>> projects.
>>
>> Yeah, I wish people would stop breaking things, and stay absolutely
>> backwards-compatible to existing designs. FPGA were supposed to make
>> hardware design easier, and then they sent in an army of programmers
>> to replace hardware problems with software nightmares.
>>
>> The *service pack* is a 300 megabyte download.
>>
>>> I've done the reprogrammable flash thing myself and I definitely concur
>>> it _can_ get a little hairy.
>>>
>>> Wish you the best of luck getting the design fully operational. What are
>>> the specs?
>>
>> Here it is. Fortunately, the hardware is in good shape, so all we have
>> to do is pound the firmware and fpga into submission. Soon.
>>
>>
formatting link
>>
>>
>> John
>>
>Nice specs indeed.
>
>If I had the money, I'd want one ;)
>
>Cheers
>
>PeteS
But hey, this is a revelation:
Hardware design has always been comforting because it is direct, simple, visible, wysiwyg, physical, and generally reliable. The tools, oscilloscopes and such, are approachable and dependable. I can use a
30-year old tube-type TEK oscilloscope to debug the most modern analog or digital circuits, without downloading and installing service packs.
Software is abstract, indirect, bizarre, and unreliable. The tools are buggy, bloated, always changing, unpredictable, pig slow, and seldom backwards-compatible. I can't use current-gen tools to edit a 2-year old FPGA design, and I'm lucky if I can somehow still find and run the older tools.
So, FPFAs, VHDL, and the associated software tools are the trojan horse that's finally letting the software people get revenge, finally allowing them to force us hardware designers depend on (and endlessly pay for) their bizantine and unreliable methodologies, to trap us in the gotta-upgrade-but-every-generation-has-more-new-bugs loop.
And the new Windows-based scopes and logic analyzers, of course... same idea.
John