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Hello all,

I'm curious to know the benefits of using third party synthesis tools. For
example how much better are synthesis tools like Synplicity or Synplify, etc
over just using the vendor tools ISE Webpack. Do you only experience some
significant gains with large designs or does it not really matter. I've been
using the Xilins synthesis tools for quite a while and have never had a
problem. I will be the first to admit that my largest designs have only
taken up about 60% of a XC2S150 so I'm not dealing with mosterous designs.

Anyn commetns are appreciated.

Jason

snipped-for-privacy@remove.sympatico.remove.ca

remove the removes to reply to me personally.



Re: Quick question
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search back through previous posts on synplicity, I recall several
posters have said that they were getting better results than webpack
on the larger designs, which I can believe although for now webpack is
fine for me too.

regards

johnjakson_usa_com

Re: Quick question
I see you're not pushing density yet.  Are you pushing speed?  If your needs
are for slow clocks, low complexity, and low density, you shouldn't need
anything more than you have.  Other third party tools can provide higher
speed performance through better optimizations that have sensitivity to
which paths are more critical than others.  When it was first coming out,
XST (Xilinx Synthesis Technology) was heralded as a nice, technically
accurate compiler that will always have access to the latest silicon
features.  Its purpose was not to provide spectacular performance results;
for the points where it does outdo third party tool vendors, kudos!

I have a design now where I know where my worst delay will be and my coding
style is attempting to coax the critical signal into the last layer of
logic.  My expectation is that the 3rd party synthesis will deliver good
results to begin with and only need a little tweaking to get the worst
behaving paths under control.  I'd expect much more interaction with XST to
be able to achieve similar results, but this is a guess;  I haven't USED the
tool, only listened to their FAEs.


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Re: Quick question
My recent task had me interacting with XST and altering the settings to
highest effort to achieve the timing constraint that I had. I eventually had
to use the reentrant route feature to finally make the constraint. I would
imagine that using some floorplanning might have helped me out, but as I
have yet to get into the basics of floorplanning yet I felt to try and just
push the tools more. Since I brought it up, do you use floorplanning when
doing a desing, and if so, where is the best place to start. Is the idea to
get things as close as possible keeping the routing as short as possible, or
just to focus on specific areas that might use faster clocks, and require
short delays?


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Re: Quick question
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If you need to resort to placing your logic, I'd suggest you first consider
RPMs - relationally placed macros - to deal with critical paths.  If you
have a 25MHz clock that has one flop that always goves you troubles, the
paths that drive that flop may be more routing than logic.  A good rule of
thumb for "decent" routing is 50% routing, 50% logic as reported by the
timing analyzer.  If you're at 60% logic and you're still having troubles
meeting timing, look seriously at ways to redo the logic.  If you're at 70%
routing, RPMs can place critical components within that path closer together
without tying them down to an absolute slice.  I'll use explicit LOC
location constraints on signals that interact with the I/O cells that have
been LOC'ed for my PCB pinout but for logic-to-logic paths I typically use
the RLOC relative placement constraints.

As far as using the floorplanner tool, I haven't because of early bugs when
the tool was first coming out.  The user constraints file can include
everything you need; you can often put the constraints in your source code
if you find that a better place to document your placement constraints.

In general, you will get better results if related logic is confined to a
specific area of the chip using the AREA_GROUP constraint on a module;
several wildcard-selected signals can also be kept in a small range to help
meet timing on particular paths without resorting to RLOCs.

There are many ways to skin the cat.  Sometimes it's the place & route
that's giving you troubles.  Sometimes it's the synthesizer that's throwing
in 7 levels of logic onto a critical signal that could have been included in
the last level of logic.  It's times like that that it's better to recode to
coax your synthesizer or seriously look at a new synthesizer that will know
better in the first place.

Timing is often the most annoying part of high performance design but the
results from attention to detail can get you into a lower speed grade device
or a higher margin design.



Re: Quick question
Thanks for the tips, these are the little things you don't find in the
manuals.

Jason

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Re: Quick question
We think we can give you a good sized advantage on both area and timing.
Our area advantage tends to be even bigger than our timing advantage which
could get you into a smaller part.

We also have some good analysis tools that can help you figure out
how to improve your RTL - a good clean design always helps.

- Ken McElvain
CTO, Synplicity, Inc

Jason Berringer wrote:
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