S/w used : Xilinx WebPack Chip : Spartan - XC2S200PQ208C
I have configured a bus as a bi-direction by declaring it as 'inout' However on synthesizing the verilog files, the constraints editor shows some of the bus lines of the bus as BiDir and some as Tri Output
Is there any reason all the lines are not BiDir? What could have forced some of the line to become TriOutput?