Hi everybody,
I am having a problem with one of my designs on Virtex II. I have been trying to get this working for quite some time now ( I have generated around 50 BIT files by now) and have not yet got it :( I have noticed that the BIT files I generate do not behave consistently (most of the times it's working erroneously). i.e if I make some small modification and regenerate the BIT file it goes haywire. I am just sending out a constant data through a mux and some registers. The data gets corrupted. This I observed by connecting the outputs to a logic analyzer. I also am using ChipScope and I can see that the data gets corrupted even as seen in ChipScope. Currently I am suspecting things like -
- The DCM I have used to multiply an input clock by 2X. (I use the multiplied clock all over the design.)
- My timing constraints, because, some of the corruptions I observed hint at clock skew > Data delay.
- A high fanin MUX in the data path.
But ISE is not giving me any errors/warnings in this regards. It says all constraints met as seen in the TWR file.
Is this a known issues of somekind! I can post more details(what?) if somebody can analyze the specific nature of the problem.
Any information regarding this would be greatly helpful!
I looked through some of the older posts in this groups which talked about clock jitter. One thing I have to do is - I have to look at my input clock jitter spec. I definitely need more info :)
Thanks and Regards, Swarna