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Overriding a VHDL generic for command-line driven synthesis with ISE

Hi friends

i have a question regarding ISE Webpack (7.1 to 9.1 versions): Is it possible to override the value of a VHDL generic (e.g. for the top-level module under synthesis)??? Does there exist such option that can be be applied either interactive or from command-line (or both?)

This would be a very useful feature and other synthesis tools (for ASICs) do have such option.

Thank you in advance

Nikolaos Kavvadias

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Uncle Noah
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