Hi
I have a design in which ADC data is clocked into a Virtex II using a clock provided by the ADC chip. The ADC data lags the rising edge of the ADC clk by 13 ns. In order to compensate for this delay, I use a fixed phase shift in a DCM to generate the clock on which the data is registered and the internal logic runs. After registering and processing the ADC data, I send it off the Virtex to external SRAM chips which are clocked by the DCM'ed and phase shifted version of the adc clk. I would like to create the constraint that data to the SRAM must be valid 5 ns after the clk edge of the internal adc_clk (which has been DCM'ed and phase shifted). I tried as shown below:
TIMEGRP "SRAM_DATA" OFFSET = OUT 5 ns AFTER "pad_adc_clk"
The Xilinx timing ananlysis tools take the phase shift into account, reporting errors in the post map static timing. The phase shift in the DCM shows up in the fact that the source clock is reported as being at 6.5ns instead of 0ns. This makes perfect sense. My question is this: what is the best way to create an OFFSET OUT constraint that takes the phase shift into account? Should I add 6.5 ns onto my original constraint (ie. "out 11.5 ns after pad_adc_clk") ? I can't use the clk0 output of the DCM instead of "pad_adc_clk" because "An OFFSET specification must use a pad signal to designate the clock" (quoted from Xilnx ISE error message ;) )
Many thanks
Sam