I hope one of the Xilinx gurus can help me out here...
I've got a design that uses multiple V2Pro parts receiving a common high speed clock. The clock is well laid out to equalize trace lengths and is differential. I also have the ability to cleanly start/stop the clock.
I'd like to use the CLKIN_DIVIDE_BY_2 option on the DCMs in the V2Pro parts to cut the rate down, but I'd like to make sure that the CLK0 outputs of the DCMs in the different parts come up in phase.
For this design, I'd hook the CLK0 output to the DCM feedback pin in each FPGA.
If I stop the input clock, reset the DCMs in each part, then start the input clock again... a) Will the input dividers of the DCMs be in phase? b) After the DCMs achieve lock, will the CLK0 outputs of the DCMs in the different parts also be in phase?
Thanks!
John Providenza