Multiple PicoBlaze/Bus access

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My design has 2 PicoBlaze processors on a Spartan-IIE sharing a common
planning to use simple priority based bus arbitration. Now I am trying
to figure out the minimal changes I need make to the PicoBlaze core in
order for the IO logic to be bus aware. It needs to assert BREQ to
request the bus, wait until BACK, use the bus, then deassert BREQ to
release the bus.

Any suggestions are most appreciated. Any resources I can look at?


- Abdul

Re: Multiple PicoBlaze/Bus access (Abdul Nizar) writes:
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If the bus is simple (as in a single cycle per operation), another
approach is to alternate between CPUs and make each CPU stall if
it needs the bus at the wrong time.

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