Hi,
First of all, thanks for your reply.
Certainly, I've got some stuff to deal with, as can be read from the warnings that I get. I am posting them here, asking for your kind guide on what should I apparently correct, what errors are inferred from these warnings. In advance, please apologize for the long post.
From the Synthesis report, I get the following warnings / infos:
WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 19-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 19-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal .
-- trimmed
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
-- trimmed
Found area constraint ratio of 100 (+ 5) on block memtest, actual ratio is
- FlipFlop presentState_FFd1 has been replicated 3 time(s) FlipFlop presentState_FFd3 has been replicated 1 time(s) FlipFlop presentState_FFd4 has been replicated 1 time(s)
-- trimmed
-----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+ clk | BUFGP | 9 | _n0029(_n00291:O) | NONE(*)(rd) | 3 | _n0030(_n00301:O) | NONE(*)(addressint_12) | 19 | _n0031(_n00311:O) | NONE(*)(status) | 1 | _n0032(_n00321:O) | NONE(*)(diffcount_2) | 19 | _n0033(_n00331:O) | NONE(*)(direction) | 1 |
-----------------------------------+------------------------+-------+ (*) These 5 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.