I am trying to load a EDK design in modelsim for simulation.I can successfully compile the files but when I try to simulate the project, I get the following error.
# Loading /home/simulation_library/simtemp/unisim.ppc405(ppc405_v) # ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns). # Time: 0 ns Iteration: 0 Region: /system/ppc405_0/ppc405_0_ppc405_i # Loading /home/simulation_library/simtemp/unisim.ppc405_swift_bus(ppc405_swift_bus_v) # Loading /home/simulation_library/simtemp/unisim.ppc405_swift(smartmodel) # Loading /home/downloads/modelsim5.8d/modeltech/linux/libsm.sl # ** Error: Failed to find LMC SmartModel libswift entry in project file. # ** Fatal: Foreign module requested halt. # Time: 0 ns Iteration: 0 Instance: /system/ppc405_0/ppc405_0_ppc405_i/ippc405_swift/ppc405_swift_inst File: /home/Xilinx/smartmodel/lin/wrappers/mtivhdl/smartmodel_wrappers.vhd # FATAL ERROR while loading design # Error loading design
I have followed the Xilinx website answer links and followed the steps exactly.