Microcontrollers have a better predictable time behaviour than FPGAs

Jidan, If you're gonna post your homework questions, please do us the courtesy of posting from somewhere else other than tuwien.ac.at. Thanks, Symon.

Of course : One is Hard, and one is Soft, how can something that is soft have "a better predictable time behaviour" ?

You can find other examples to prove this in the data sheets too:

Look at the uC with 1-2% OnChipOsc Specs, and then look for any tolerance specs on the FPGA on chip Osc.

Again, uC clearly have "a better predictable time behaviour".

You should win this debate easily.

-jg

Please don't feed the monkeys. They're getting a balanced diet from the zoo-keeper already.

In news:4662dab4$ snipped-for-privacy@clear.net.nz timestamped Mon, 04 Jun 2007 03:15:14

+1200, Jim Granville posted: " snipped-for-privacy@hotmail.com wrote: > "Microcontrollers have a better predictable time behaviour, because > their circuit is integrated in silicon and is unchangeable; unlike > FPGAs which have variable timing performances." >

Though not necessarily about microcontrollers, it was argued that newer processors are less predictable than FPGAs in M. Ward; N. C. Audsley, "Hardware Compilation of Sequential Ada", CASES 2001.

snipped-for-privacy@hotmail.com schrieb:

You could also try to compare a house with bricks. Yes, you can build a house out of bricks (but also out of something else, like timber). And yes - if bricks are fixed to a structure, that we call a house you can compare it with a house made of timber - or even with a brick-wall.

A FPGA is like bricks and a microcontroller is like a house in this comparison.

Ralf

I don't know, because it's nearly meaningless.

What I *do* know is this: Once you've successfully implemented a given function or circuit on an FPGA, its timing is entirely predictable in the sense that every copy of that FPGA will meet the same timing spec - maximum clock frequency, input setup time, output delay, etc. In a rather similar way, every microprocessor chip of the same type that you buy will meet its data sheet timing spec. So in that sense, the statement is nonsense because FPGA implementations and microprocessors are equally predictable at meeting their timing specs.

I also know that a typical microcontroller represents a large investment in design and verification work by the manufacturer, work that I would have to do myself if I wished to implement exactly that microcontroller in an FPGA. So I'm not going to bother to do that. I'll buy the uC chip, thanks - unless the uC function can be trivially integrated into my FPGA using the nice system-builder tools currently on offer.

I also know that I can design things in an FPGA that will outrun a microcontroller by many orders of magnitude in speed. And here we perhaps get to the nub of your statement, because until I embark on the FPGA design I can't know exactly how fast it will run - what its Fmax will be. In that sense, and only in that sense, the FPGA is "unpredictable". However, modern timing analysis tools, combined with my own engineering intuition about which parts of the design are most likely to be timing-critical, will quickly lead me to a good estimate of the speed that I will ultimately achieve, and therefore will guide my design strategy so that I can meet my application's requirements.

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Thanks for the informative answers. Lets say I implement a core processor on a certain FPGA, e.g. Spartan-3 XC3400, and figure out the timing speicifications. Later, I want to implement this same core in the same FPGA series only bigger, e.g. Spartan-3 XC 3S1000; how accurate will the timing specifications I did in the previous FPGA be here?

snipped-for-privacy@hotmail.com wrote: > Thanks for the informative answers.

As long as the speed grade and the FPGA family doesn't change, the achievable maximum frequency should be more or less the same. But it depends on how big the core implemented is. If it fills up a large portion of the FPGA, the tools might not be able to place and route everything in the most optimal way, because they have a hard time squeezing the design into the FPGA in the first place. In such a case, the design will perform better in a bigger device.

HTH, Sean

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