LVPECL, Virtex II and the EP445

First, the FPGA banks would need to be at 3.3V. Then, you could:

1) Use two FPGA inputs (P/N pairs) per LVPECL output. The N side of one of the diff input pairs would be biased to the common-mode level of the LVPECL output. The drawback of this is that it will take 128 FPGA input pins.

or

2) Use SSTL3 inputs and tie all the VREF pins to the bias point (the common-mode level of the LVPECL outputs). This will reduce the total number of FPGA input pins required.

Bob

Eewww... Thanks for the info, though. I'll ponder these two. The 128 inputs is fine because if there were a version of the 445 with differental outputs, I'd buy it. My resistance to using buffers to make them differential was the number of external buffers I would need.

The SSTL3 is an intersting idea.

have

Howdy,

That is a bit of a toughie. Spec's for the EP445:

Voh is between 2155 and 2540 mV. Vol is between 1355 and 1740 mV. Min Swing ~800 mV, although typical looks to be closer to 850 or higher.

Looks like the output is normally centered around ~1950 mV, although spec shows it could be as low as 1790 or as high as 2115.

As you probably know, this doesn't match up with any of the "normal" standards. I'll bet you could abuse the GTLP or single-ended SSTL or HSTL modes to get the job done by adjusting the vref and vcco values up to the values you need for this, although all of those standards have very small hysteresis.

So you might be able to get away with AC-coupling the signals and re-biasing them, in which case not only could you perhaps use the above input types, but also maybe a PCI or LVCMOS1_n input type?

Or as Bob posted, you could go ahead and chew up 2x the number of pins and bias the _n input of a differential receiver to the mid-point.

Good luck,

Marc

For this you have the VBB output on single ended ECL devices. Indeed

3.3V SSTL has the highest VREF and should suit best with one EP445 connected to one IO-bank with VBB connected to VREF. I once saw an app note were they used resistor dividers to get from PECL to LVDS. This could be done either to accomplish true SSTL levels but might degrate speed. One might just have a look ar

That's no problem as long as your VREF is ok.

From performance point of view this is best if voltage translation is required, but requires DC balanced data patterns.

The advantage of using seperate VREF pins (that's basicly what you are doing) could be that the IO bank restriction falls. But even on parts with high IO count banking shouldn't be a problem. I'd prefer single ended connections (from the EP445) from the PCBs point of view.

Regards Thomas

This is probably best as I was prepared to do that anyway in the parallel univered where On Semi made the outputs of the 445 differential. ;-) It's an XC2V4000 in a BF957 package. It's the 64 signals in and then another 64 out on the far side. That's 90% of this chip's I/O. The rest is just control lines and a serial data link from another FPGA.

Thanks for the tips, guys.

pins

this

from

Reminds me of a new 4VFX60 design that we've started... 40 general purpose I/O pins (all CPU and clock related) + some RocketIO channels. The ideal package to allow movement to a larger device if neccessary, would be the FF1152 pkg. Talk about having a few unused pins!

Have fun,

Marc

I haven't used any of them recently, but I think there are several

1-10 Gbps shift register/demux parts with diff. outputs available, from the other usual suspects ( Micrel/Vitesse/Maxim/etc. )

Brian

Yeah, looked through all those before settling on the EP445. A lot of those are either overkill for my input, only 1:4 or they're really only good for SONET rates.

What I want is a programmable 1:N and N:1 serializer, deserializer pair of chips with N = 2 to 16.

only

pair

For what data-rate(s)?

Marc

Up to 3 Gbps on the fast side.

Oh, and programmable logic levels, too. :)

My currrent design is getting NCML from the upstream units.

NCML. There's three other people in the world using NCML as far as I can tell. High level is 0 V, low level is -0.5V. Who invented that one?

Thank goodness for On's Gigacomm parts. With differential signal they take almost anything from 0 to -2V.

Those "any level in" buffers would be real nice in an FPGA. Hint, hint, Xilinx.

And I want to go into an FPGA at 3 Gbps without any special Rocket I/O stuff.

And as long as I'm dreaming, I'd like a pony.

Dear Pony Dreamer, So, I guess I use NCML except that I call my ground signal 2.5V! Seriously, there are lots of designs out (t)here with 'ground' planes at voltages other than 0V. Maybe that's something you could consider.

Micrel make some similar parts to the On Semi ones, have you seen them?

As for 'any-level-in', you'll find that Xilinx parts have a very wide common mode range for their LVDS inputs. They stop working at sub-Gbit rates though, I reckon all that other single ended crap attached to the same pin makes the capacitance too high for anything faster. Does Rocket I/O help?

I hope some of this waffle helps! Cheers, Syms.

Just measured a Spartan3. In LVDS mode the inputs work nicely over a common-mode range of < 0.2 to *over* +3.3. I suspect the single-ended modes would work with a Vref in that range, too.

John

Hi John, Wow, that's better than I expected! I'm pretty sure that there's no accurate spec for Vicm because otherwise Xilinx would have to test the inputs meet timing and Vid over a large range of Vicm. Thanks for the heads up mate, Syms.