I have been doing FPGA design work for a few years now and must admit that timing analysis scares me because it is something I didn't learn in school. We use Xilinx FPGA's at the company where I currently work, and I am somewhat familiar with the ISE Timing Analyzer tool. However, I am looking to learn how to do timing analysis manually before using the tool, because I feel it is becoming more and more important as bus speeds are increasing, not to mention it's a good skill to add to a resume. Can anyone suggest any resources, whether they be online or perhaps a good book? I'm looking to have an understanding of the various parameters one must take into account when analyzing timing budgets for both system and source synchronous interfaces, including board-level effects. Any information would greatly be appreciated.
- posted
17 years ago