ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)

I find that using the PowerPC allows a very convenient method of running interactive tests via a serial link. It certainly is not necessary for using the RocketIO.

The Aurora core is free, and the license has very little in the way of restrictions. It is also very easy to use, and should in my opinion be your first choice for a plain data interface.

It would probably help to understand how you wish to use the interface. Are you actually attempting to implement the Fibre channel protocol, or do you mean that you are using fiber optic cables.

You need to read the "RocketIO Transceiver User Guide". That is all covered. Also, the Avnet board reference design comes with a UCF file with the correct pinouts.

Hi Duane,

1. The reference design is power PC based and includes the BERT test. I do not want to use that. So I thought of using the Rocket I/O implementation on the logic fabric. Also I am using the fibre optic cable. What specs to use for that?
2. The ucf file that comes with the Avnet board is for the EDK project. I am confused about converting it for ISE project.

At the same time, thank you for letting me know that the Aurora core is free of charge. Let me download it and look into it. Thanks, Vivek

Duane Clark wrote:

Fibre Channel is a protocol, and a rather complicated one at that (and it does not necessarily require fiber optic cables). A fiber optic cable can use any protocol you want. Aurora defines it's own protocol, which is a very simple one suited for basic data transfer. It sounds like that is what you want to do.

The Avnet ucf file has the pinouts used on the board, and that is not dependent on whether it is an ISE or EDK project. You can copy those pinouts to your own project ucf file, changing the signal names to whatever you intend to use.

Hello Duane, thanks for the reply. What I meant was that the constraints for clocks can be used for the ISE file. However I get errors while trying to define :

INST GT_FIBRE_CHAN_INST/mgt_io/mgt_io_1 AREA_GROUP="BERT_0_GRP"; AREA_GROUP "BERT_0_GRP" RANGE=SLICE_X0Y0:SLICE_X33Y59; #---------------------------------------------------------------- # MGT Placement: #----------------------------------------------------------------

#Top MGTs INST GT_FIBRE_CHAN_INST LOC = GT_X1Y1; ## MGT6

Any > Vivek Men> > Hi Duane,

When you sign up with Xilinx for the Aurora core, you will receive a license to use in Coregen to generate a core. When you generate the core, along with the design files, a constraints file will be generated that has all those constraints. You will copy those constraints into your ucf file. The core comes with docs explaining how to use it. I'll admit that the first time you use coregen to generate an Aurora core, it can be tricky trying to figure out what to enter, so you can ask here if you have questions about that part.

Hello,

Thank you Duane for the pointers. I did get the first design to work on Aurora (eg. counter design). I am going to try sending the actual data.

However, I have some doubts again:

1. I need to send a data pattern at a very high rate. The Aurora links transmit data at 3.125 GBits/sec ( multiplication of Bref_clk with a factor of 20 inside the DCM). I was wondering if I could access that clock and use it clock my data generator module.
2. Moreover, has anyone accessed the data sent through the Aurora links on a high speed oscilloscope. I am trying to send modulated GPS signals and hence this query.
3. I have downloaded the Aurora module and I am using it to implement the networking among a series of FPGAs. Is Aurora proprietary?? Can it be used by the industry for implementation on their products??( I want to know if it's restricted to academia use.)

Thanks, Vivek

Duane Clark wrote:

In the Aurora core user guide, there is a chapter on "The Clock Interface and Clocking". Notice that there are clocks generated called USER_CLK*. You can use those clocks with any extra logic you want. At least in the user guide ug061.pdf, Figure 7-2 shows this connection.

If you have a scope capable of handling these signals, sure. People use eye diagrams on a scope to determine how much margin a link has. Also, it was my understanding that Xilinx used to have centers scattered around, at least in the US, where a company could bring in a board and check out RocketIO interfaces on their equipment. I assume they still provide that service, though I never used it myself.

For myself, I tested the links by generating a known pattern on one side of the link, and had hardware detect the pattern on the other side and count bit errors. You should have no bit errors on a good link. Test your detection code by including the ability to inject an occasional deliberate error.

It is not restricted to academia, but other than that I can't give legal advice ;) The core came with a license agreement, and despite the legalese, you should be able to figure out what is allowed.

use >>those clocks with any extra logic you want. At least in the user guide ug061.pdf, >>Figure 7-2 shows this connection.

I did look at this figure but I guess I should have framed my question differently. Is the user_clk multiplied by 20 inside the DCM present inside the MGT. When I try to use a DCM to multiply it, the maximum I can shoot for is to 250 MHz. So how can I use the user_clk as it is still 156 MHz and are there any other ways to access the multiplied clk signal?? ANy pointers??

Vivek

and >>Clocking". Notice that there are clocks generated called USER_CLK*. You can use >>those clocks with any extra logic you want. At least in the user guide ug061.pdf, >>Figure 7-2 shows this connection.

The x20 multiplier is indeed already inside the MGT, and is produced off the "dedicated" REFCLK/BREFCLK. That is why they are so picky about how you provide that clock. You don't need to provide x20 clock, and you don't have any access to it. It wouldn't do you any good; even Xilinx FPGAs won't run at 3.1GHz yet.