Eilert,
The main purpose of this code is to recognise when 'input_signal' is high and then set 'output_signal' high and then wait for 'output_complete_signal' to be high before setting 'output_signal' low.
The complexity comes into it where 'input_signal' is accompanies by a data signal and depedant on that data one of many 'output_signals' are set high and a corresponding 'output_complete_signal' is monitored instead. However, the structure of the code is the same, just expanded.
Answer, I don't want a 'shift-register' and am not familiar with the functionality of a 'priorty-encoder'.
The behaviour that you described is exactly how I intended it to behave.
The behavioural simulation operates correctly, I have not done a timing simulation (and cannot for other reasons).
Regards,
Simon