architecture Behavioral of tsb is signal fo1, fo2 : std_logic; signal data0 : std_logic_vector(3 downto 0); signal data1 : std_logic_vector(3 downto 0); signal data2 : std_logic_vector(3 downto 0); signal data3 : std_logic_vector(3 downto 0); begin process(clk) begin if clk'event and clk = '1' then data0
- posted
17 years ago
3 parts partial products multiplier tap;LMP Adaptive Filter;Direct form fir filter core but quartus report that: Error (10334): VHDL error at tap.vhd(82): entity "tsb" is used but not declared
2 sections related to "tsb":