help for Viterbi decoder design

hello, i am doing project on implementing viterbi decoder on FPGA. i know theory about Viterbi decoding. i dont know anything about FPGA. can body can help regarding this by telling how i can approach for that. thanking you.

Reply to
sunil
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Well, first off all, I would suggest that you "just start" writing the decoder. Do it the best way you know how to. And than see where you get stuck. There is nothing special about FPGAs (unless you want to use some special functionalities like DPLL for example).

Once you make some sort of an effort and can show people where you are stuck, you will get lots of help and support from other designers.

Also visit

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and join the cores mailing list. Once you have made an effort and can demonstrate the problem you are having, I'm sure many people will be happy to help you !

Good Luck !

Best Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores ->

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Reply to
Rudolf Usselmann

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