I had a question about the latest happening in this market. Since I am new in this area excuse me in advance if the question sounds stupid.(:-. What is trend for programming devices now a days. I mean are people using VHDL/Verilog more and more for design or they use design tools such as Orcad etc. What is better off the two. What are the pro/cons of using VHDL/Verilog in comparision to schematic capture. Thanks
IMO, VHDL/Verilog is used by professionals who work moreless fulltime with this stuff. The schematic approach is much easier when you come from the hardware side. What is more and more becoming used is somewhat unnecessay as it involves the sales to occasional users.
Rene
-- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
as simple as this:
ALWAYS use Verilog/VHDL
NEVER use schematic capture
those who come from ASIC/FPGA world would probably agree.
but honestly, the only place where you might use schematic capture would be a small, very well defined project with knowing that the flexible design & fast design time is not an issue.
yet the speed of the design process + its integrability with some other people like me, who really hate schematic capture, because the warnings generated during synthesis are annoying and i most cases cannot be avoided.
Vladislav
That's kind of like saying:
ALWAYS code in Java NEVER use assembly
I think better advice is to use the appropriate tool for the job. Schematics have their place. In 20 years, HDLs will fall out of fashion and we'll have a schematic renaissance. These things come and go in cycles. I see a lot of bell bottom trousers lately. And there seems to be an uptick in serial "expansion busses" in personal computers. It sounds like the
1970's have returned.Eric
hehehe guys I think I have started a pretty good discussion here. However I am not complaining because I am a novice in this field (actually a week old) and its very enlightening to read everyones point of views. Thanks a lot for your inputs.
renaissance.
Do you mean that in 20 years Java will fall out of fashion and we'll have a assembly renaissance?
Another disadvantage of schematics is that they are generally in a proprietary format. Which means an old design might not be readable in the latest version of a vendor's schematic tool, while a text file is forever. Also, targeting a different vendor's fpga usually means re-entering the schematic from a different symbol library, while HDL is retargetable with much fewer changes (like none if you're lucky). And thirdly, simulation of a schematic based design is 1-2 orders of magnitude slower than simulating RTL VHDL. The difference between 1 minute and 30 minutes in the iterative design process is huge.
Jeff
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