Fixed point number hardware implementation

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Hi KJ, I've visited the site VHDL.org and read the following:

and

and i think the stuff on Accelera website is also the same apart from som nice powerpoint presentations. I could understand the logic behind these packages and they sounds reall very good (especially in my case) I mean positive and negative indices hav been used to differentiate the integer and fractional part. That's great But, I can't understand how to compile and add these packages to m library? Do I need to use Modelsim for this purpose or Xilinx? I mean how to compile it? Do I need to copy the .vhdl files of thos packages in the IEEE folder or vhdl source folder where some othe libraries are or what? I'll be very thankful if you could give me a direction at least, Thanks, kami

If you haven't simulated the filter in fixed point arithmetic, then you are not ready to implement the filter in VHDL. Did I understand you correctly?

When you want to design a real filter instead of a paper filter you have to pick additional parameters like number of bits in the coefficients, the data path and any retained accumulators. These decisions all affect the accuracy of your filter and need to be tested in the simulator before you try to implement it is an HDL. Then the VHDL step is just a matter of coding what you already know works.

Rick

If I recall correctly, they expect to be compiled into an 'ieee_proposed' library.

Depends what your purpose is. Modelsim is used for simulation, Xilinx is a big company that sells FPGAs.

Put the source files wherever you want to. Then compile those files. If you don't know how to do that then perhaps you need to understand what tool you're using first and should go to the manual for that first.

Head in the direction of the manuals for the software you are using.

KJ