I'm a hardware design engineer with 10years background in FPGA design. To date all my design entry and simulation has been with VHDL but I seem to keep having to type similar (but not identical) ram instantiations/ state machines/ clock domain re-synch processes etc. This ends up a bit tedious and I've been wondering how to circumvent the tedium.
I've been looking at the grahical state machine entry facility of Modelsim Design and wondering if it's any good and would end up saving any time. I suspect not or the software industry would have adopred this sort of design entry method years ago.
This started me wondering what the favourite design entry optomisation methods of our experienced comp.arch.fpga contributors are? Has anyone had any success with graphical entry?
Nial
------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board