Downloading into XCV600

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Hi Fellows,

I have main architecture consists of different components. All these
components are defined in different *.vhd files and I am combining all
these VHDL files in one *.vhd file and downloading into the CHIP and
it's working fine according to logic. Lets  call this main BLOCK as
BLOCK1.

Now,I need 6 of these blocks on the same chip (I am using XCV600
device). And I need to interconnect different signals defined in the
BLOCK. say for example I need to loop all of them together.
How could I accomplish this task. I want only one *.vhd file so that
it would be easy to download one *.rbt file into the chip at one time.

1. Do I have to define different input / output signal so that every
BLOCK has different signal names from each other and than use port map
and component decelartion in top *.vhd file to accopmlish the task.
Thats how all these *.vhd files  would be in one *.vhd file. For
example in one BLOCK I have 4 entity/arch for 4 components and 1 main
entity/arch where port mapping and component decleration is defines ,
so I have 5 entity / arch in one BLOCK and it's in one *.vhd file.
Thats how for 6 of these BLOCK I would have 30 entity/arch + 1 main
entity/arch in which all of these components (which I think 6 one of
each BLOCK)will be defined along with port mapping.
So in all 31 entity/arch pair would be in one *.vhd file. Do you think
is this correct. Or is there is any other better way to do this.
2. How can I use make file option to compile 6 different *.vhd files
(one of each block )and 1 main *.vhd file (for component decleration
and port mapping)
to generate one *.rbt file.

I am worried because I have to use 12 BLOCKS of different logic design
having 12 entity/arch pair block (in all 145 Entity/arch pairs )and
interconnect all these 12 block with 6 above mentinoed BLOCKS.


Cheer Guru's

Any help would be appreciated.

Isaac

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