Hello,
I am somewhat new to vhdl, xilinx, etc. The board I am working with is the Spartan 2s50-pq208-6. I have created my design in VHDL and went to assign the pins. I have a signal "reset" that I need to drive off of one of the boards switches.
The problem is that XILINX has determined that the "reset" signal is a global clock signal and can only use of the the 4 global clock signals on the board.
How do I prevent this from happening.
I am using Xilinx Free Webpack 6.3.
Since I am new to all of this, I am not sure what to post. Here is my code: entity prj2v3 is
--d comes from MC
--p comes from peri port(ceAL, a0, rdAL, wrAL, reset, stbAL: in STD_LOGIC; ibf, intr, bufctrl, here: out STD_LOGIC; d: inout STD_LOGIC_VECTOR(7 downto 0):=(others=>'Z'); p: in STD_LOGIC_VECTOR(7 downto 0)); --attribute syn_noclockbuf of reset : signal is true; end prj2v3;
architecture Behavioral of prj2v3 is
signal ctr: std_logic_vector(0 to 1):="00"; --ctr.0=MODE ctr.1==INTE signal str: std_logic_vector(0 to 2):="000"; ---str.0==IBF str.1==INTE str.2==INTR signal data: std_logic_vector(7 downto 0):="00000000";
--signal here: std_logic:='0';
--signal here2: std_logic:='0'; begin ctr(0)