Design question (Working with Altera EPXA1F484C1)

I have a question about how I best should implement my I/O in an FPGA (Altera EPXA1F484C1) . Being a student, and not having a whole lot of people to ask for advice, I have no idea how I best should solve my problem.

I initially wanted to have 128 + a few inputs and 128 + a few output pins, so that I could work in parallell on 128 bit blocks.

This didn't work, apparently because I had used to many pins. Quartus (II 3.0) gave said in it's report that I had only used 258 of in all 292 available pins, but I suppose I had used all available general purpos I/O-pins or whatever. I scaled down my design, until I got to compile it. At that time I was using 186 pins. And I when looked at the floorplan, every row and column I/O-pin was in use. So I guess 186 pins is the maximum limit.

So my first question is: Why can I only use 186 pins, when Quartus tells me that there are 292 pins available?

So I had to decise how I would send and recieve my data. And this is my main question, my design question:

Would I be best off using say 64 pins for input and 64 pins for output, and solve my problem that way, or could I use a bidirectional solution, where I alternate on recieving and sending data over a 128 bits bus?

I put together a test-design wich utilizes this solution, and it compiled fine. I put an image of the schematics on a website, so you can take a look:

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But is this an sound solution?! Or should I rather go for separat in- and out-pins? Since I have no clue, I have to ask someone. And you guys drew the shortest straw ;-)

-"Panic"

Followup to: By author: "Panic" In newsgroup: comp.arch.fpga

Impossible to tell without knowing what your application is, i.e. what "SubBlock" contains. Typically, a bidirectional bus will provide higher throughput in any one direction, but it costs time to turn around. Thus, if you are continuously processing data (let's say that you're doing an AES stream encryptor), you'd be better off with separate input and output busses, even at half width, but if you will be communicating in one direction at any one time then one bidirectional bus will serve you better.

Also, in the case of the split bus solution, consider whether or not it is practical in your application to double-clock the 64-bit busses.

-hpa

-- at work, in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64