Hi
I have a simple question. I have a design where the RTL simulation is working. Now I would like to see if the design also works then on the FPGA. The obvious way would be to use the JTAG interface and see what is going on in the CHIP. Anyway, is there somehow another way this could be achieved? For example is there somehow a way that a file could be written to which I can get them someway access? Or is the JTAG the only option I have?
Cheers Paul