1. Home
  2. Field-Programmable Gate Arrays
  3. DDR simulation

DDR simulation

I have a problem when simulating with samsung ddr behavioral model, I have tested my design with micron behavioral model but micron is not accurate regarding the tDQSS time constraint. so I used the samsung model, but I don't know why the DQS bus in write transactions goes to X

state. it seems that the behavioral model tries to force on the DQS while the controller tries to force on the DQS. so the result goes to X

state. I am not sure, my design is in VHDL and the samsung model in Verilog I uses ModelSim 5.5e PLUS to do the simulation I dunno where is the problem, can anyone help?

Reply to
ibrahim_magdy_ibrahim
Loading thread data ...

Hi,

I am guessing you have the classic test bench where the inputs to the unit under test (UUT) are being changed precisely at a clock edge???? This results in the indeterminate ("X") state.

If your test bench is in Verilog then an extra #1 at the start of your initial block with respect to the clock generating loop should fix this.

For VHDL testbench a "wait for 1 ps" or something similar should do.

Enjoy,

Tim

Reply to
Tim Good

Hi

I have used the MICRON verilog model for my simulation...

- MT46V32M16 (8 Mb x 16 x 4 Banks)

- Micron 512 Mb SDRAM DDR (Double Data Rate)

it worked fine in simulation, no problem with tDQSS and then it worked on the card ;O)

one thing I suggest is just make sure you simulate your Clock2Out, Pad to Clock, DCM skew, PCB delays and all that stuff

Maybe your DDR controller things you are actually performing a RD command...

Verilog mixed with VHDL no problem at all.

--
I.Ulises Hernandez
" I'm not normally a praying man, but if you're up there, please save me, 
Superman!" - Homer Simpson ;O)
Reply to
I. Ulises Hernandez

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.