CPU design

nice that you read it ;-)

Ok, the main reason for not using simulation was just because I had no ModelSim and the Quartus simulator was a pain (actually I started with MaxPlus II). However, I wrote my own kind of debugging device using the printer port on the PC. Clocked the design with the printer port and read back the interesting signals with a small state machine. Kind of creasy ;-)

Now, a lot has changed. E.g. ModelSim for Xilinx is free. So there is now a testbench for JOP available that you can use with ModelSim XE. For all FPGA specific parts (on-chip memories) I wrote plain VHDL models. So you can now debug with ModelSim XE and compile for Altera....

And I agree, simulation can save you a lot of time (and sometimes waste a lot of time - I still like to look on the code till I find the issue).

Martin

Hi Walter, Have you ever thought about doing a Compiler+FPGA_CPU (+Sim+Debug?) bundle ?

-jg

I did exactly this in a previous job. Picoblaze was nice, but there were things it did not have, and conversely things I would never use.

So I did the code (pseudocode first) and then designed the device to do the necessary functions at the microcode level. Because my problem domain was very constrained, I needed only 16 instructions (I like it when I get nice numbers like that as a solution) to do what I needed.

Then I wrote (well, I changed :) an assembler to program it.

Worked very well, and took about half the space of a picoblaze, including a DMAC engine (excluding the memory interface which was there anyway).

Cheers

PeteS

AHDL for a two register NOP, INC, DEC, WRITE unit

good for interruptable stack pointers

This looks like a net list or something like this. I have only ISE WebPack installed and I don't know how to display it. Do you have a picture of it?

Jim,

We have certainly thought about it. Byte Craft has done quite a bit of instruction design work on embedded commercial processors. Internally for every C compiler we create an instruction set simulator with a lot of performance instrumentation.

I expect the next round of processors will move towards multiple processor solutions to applications. Compilers and other HLL tools will be focused on application work division.

w..

Jim Granville wrote:

Sounds promising. What about debug pathways ?

-jg

Jim,

The automotive processors use a separate communication link (most are on board packet switched virtual links) to each processor brought out through a interface on the chip. (Nexus) There are support standards for this.

The asian processors that we have created support for were lockstepped simulation and hardware to extract more information for the developers.

Most of the current processors that I am seeing are using asynchronous background BDM or JTAG brought out through a limited number of pins.

Watch this space later in the year for information on the consumer products multiprocessor debug support.

w..

Jim Granville wrote:

i think ahdl custom to altera. there tool is web downloaded. could notget the xilinx tool to download after 5 attempts.

website more specific.

the zip file is current project design files in quartus II version 6, but still have to design instruction sequencing unit. thought of using an 8 cycle simple instruction execution, for a very compact IP core. also decided that modular forth in instancable blocks would be most flexible.

it is going to evolve as a 16n design, as all carry can happen along multiple instances to make any 16*n word size, but i have to decide how the program word width may or may not expand to the word size.

i hope to get wishbone and avalon bus interfaces too, but this is not my immediate priority.

i intend a serial bus standard to allow connected multicore designs, each core having 128KB memory.

does anyone know how to export a quartus project as VHDL?

cheesr

jacko

jacko schrieb:

Jacko,

you possible have to handconvert the AHDL to VHDL :( thats the reason I suggested using non-vendor HDL in the first place.

Antti