combining state machines.

Make this "recurring task" a black box with clock and start inputrs, and end output.

You then modify the other state machine to start this black-box, and wait for it to end.

You may even make your black-box slightly programmable, adding more inputs that may modify its behaviour for some extent.

Typical example:

Some automatic system that may have to wait in some definite states for different times. The black-box would then be, for instance, a presettable down counter with clock enable.

(Traffic light controller:

STATE OFF. when start order received, start down counter with a count of 10, and goto RED

RED. when count ends, start down counter with a count of 2, and goto AMBER

AMBER. when count ends, start down counter with a count of 8, and goto GREEN

GREEN. when count ends, start down counter with a count of 10, and goto RED

Best regards,

Zara

There have been a couple of occasions when I have used nested case statements, but it gets messy real fast.

Ron

For VHDL:

If you need multiple-clock "subroutines", the separate "black box" approach previously mentioned is the way to go. This may be a separate process in the same entity/arch, or may be a separate entity/arch alltogether.

If you need to collect common single-clock-cycle behaviors, declaring functions and procedures to encapsulate that functionality works very well. Synthesis tools do not like subprograms with wait statements or clock edge clauses, thus the single-clock-cycle requirement.

Andy J> CMOS wrote: