Hi all:
I'm pleased to announce the release of MyHDL 0.5.
MyHDL is an open-source package for using Python as a hardware description and verification language. Moreover, it can convert a design to Verilog. Thus, MyHDL provides a complete path from Python to an FPGA implementation.
MyHDL 0.5 has many new features, in particular with regard to conversion to Verilog. The converter automates certain tasks that are hard in Verilog directly. The Verilog output code works well with popular FPGA synthesis tools.
For a complete overview, go here:
The manual is here:
To find out the details of what's new, go here:
You can download the release from SourceForge:
Best regards,
Jan Decaluwe