To all,
I've develped a Master peripheral to connect to the Avalon Bus which interfaces a custom slave peripheral. The Master writes to the slave peripheral some data using the "writedata" line and by deasserting the "write_n" signal and asserting "read_n". The Master is a FSM, which has the following sequence; the first state was a read-mode state in which I was requesting something from the slave and then the following state is where I would like to write to the same slave peripheral some data:
STATE#1 write_n = '1' read_n = '0'
STATE#2 write_n = '0' read_n = '1'
The Avalon Bus VHDL code generated by SOPC builder with produces a VHDL stop error called: "vosq0_fifo_logic_avalonM_writedata did not heed wait";
where vosq0_fifo_logic is the name of the Master peripheral.
I have extracted the segment of the VHDL code from within the generated SOPC builder file to show exactly where this comes from. See below.
process (active_and_waiting_last_time, vosq0_fifo_logic_avalonM_writedata, vosq0_fifo_logic_avalonM_writedata_last_time) VARIABLE write_line3 : line; begin if std_logic'((active_and_waiting_last_time AND to_std_logic(((vosq0_fifo_logic_avalonM_writedata /= vosq0_fifo_logic_avalonM_writedata_last_time))))) = '1' then write(write_line3, now); write(write_line3, string'(": ")); write(write_line3, string'("vosq0_fifo_logic_avalonM_writedata did not heed wait!!!")); write(output, write_line3.all); deallocate (write_line3); assert false report "VHDL STOP" severity failure; end if;
end process;
I am trying to figure out what this actually means and don't understand why this error was generated. Anyone have any idea what this means?
Regards Pino