I am looking for a nice idea of hooking up many (12) simplified UART devices to NIOS II cpu using Avalon bus and fitting everything in Altera Cyclone FPGA. The problem I see is all UARTs are using one baudrate generator with 8 outputs for TX/RX clocks selectable for each UART. What would be the best way of incorporating such components into one SOPC? Or... maybe is there a way to make a mega-wizard component out of them with selectable number of UARTs and one baudrate generator to save space on duplicated multiple counters/dividers?