signals in compact flash

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Hi.

Now im developing a compact flash interface, but i have a  little
questions about  1 signal.

I'm  using a 8 bit data bus,   ATA mode with  A0-A1-A2 signals,   and
CD1, OE, WE, RESET and RDY/BSY signal.

My problem is about the last signal(RDY/BSY):   Is this signal  held low
between a read or write cycle (512 bytes block)?  When reading/writing a
register i'm always checking this signal, but i think is useless.

Anybody has a map of timing signals in memory mapped mode?

Thanks in advance.
Gugo






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