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Re: reducing flash size in embedded processors?
On Tue, 05 Oct 2004 22:37:39 GMT, "Wilco Dijkstra"

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In every way, actually.  It's part of a standard.  How could it be application
specific?

Jon

Re: reducing flash size in embedded processors?

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looking
a serious
microchip
run on

How about if you want fp using a non-standard format?  For embedded use, a
format with a 16-bit signed mantisa (including the "hidden one") and an
8-bit signed exponent might suit better, and be faster to work with.  There
are also often features in the C maths libraries that you don't need and
don't want - NaN handling, or a global error variable (which exists purely
because of the limitations of C).




Re: reducing flash size in embedded processors?
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Don't bother trying it.  I did, about 30 years ago, for a 3 byte
format and changed to the normal offset exponent, sign, and implied
leading 1 significand later.  The result was much faster and less
complicated, besided being compact.  The original signed
significand (not mantissa) code was contributed to the early Intel
user library for the 8080, and was publicly available there.  The
later (and much better) version was published in DDJ.

Denormals and over/underflow handling are entirely separate
matters.

However, a three byte (24 bit) real is a very useful animal, and
more than adequate most of the time.  In higher level languages it
needs to be padded out to four bytes for alignment purposes, and to
allow for substitution of other real arithmetic modules.  Such
things as logs, exponentials, trigonometric, root, etc. functions
can be built with very few operations on Tchebychev polynomials in
assembly, and greatly reduce the associated table sizes.  The
format yields 4.7 decimal digit accuracy.

--
Chuck F ( snipped-for-privacy@yahoo.com) ( snipped-for-privacy@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
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