need help with setting up echotek race++

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We have a simple system using a Sparc host, MCJ6 with 4 CEs, and a Dy4
181/712 running vxWorks with an EchoTek RACE++ I/F PMC on site 2.  The
2 RACE++ boards are connected with an ILK4P.  Here's a text-graphical
picture of it:
                 H           1
                c           8
               r     6     1
              a     J     4
             p     C     y
            S     M     D
            |     |     |
  vme slot  1  2  3  4  5  6  7  8
 ilk4 slot        1  2  3  4

I believe we may have a config file problem, although it doesn't
return an error after the configmc call.  I want to create a race++
transfer from CE2 on the MCJ6 to the Dy4 board.  I try to do a
dev_create() on the Dy4 board per an EchoTek example program but it
fails ("unable to create device").  At this point I'm doomed since
there is nothing for CE2 to attach to.  I've also tried smb_create()
on the Dy4 board with no luck.

The planned order of events is:

1) Load and install EchoTek driver on the Dy4 board
2) Run configmc from the host
3) Create race xfer endpoint via dev_create() or smb_create() on Dy4
4) Create race xfer endpoint via smb_create() or smb_open() on the
5) Create a dx_transfer
6) Transfer some data

Here's the simple config file:

# Define Host - SPARC BOARD
board VME_SBC VME_host

# Define Backplane
board VMEBUS VME_bp

# Define Motherboard
board MCJ6 mb1 vme_addr=0x10000000 vme_ws32%M

# Define Daughtercards on the MCJ6
board P2J256J mb1_dc1
connect mb1_dc1.DC_A mb1.DC_A
connect mb1_dc1.DC_B mb1.DC_B

board P2J256J mb1_dc2
connect mb1_dc2.DC_A mb1.DC_C
connect mb1_dc2.DC_B mb1.DC_D

# Define EchoTek PMC

# Define the Raceway Device
DEV EC_RACE.GEP dev_typeDE%V_AGERACE devid=3 nameEC%_RACE

# Define ILK4P
board ILK4P ILK_4

# Define the RACE++ connections
connect mb1.RWP2_1     ILK_4.RWP2_1
connect EC_RACE.RWP2   ILK_4.RWP2_3

# Define VME Connections
connect VME_host.VME VME_bp.VME_5
connect mb1.VME      VME_bp.VME_3

# Define CE's
CE VME_host.SBC host=1 ce_typeCE%_HOST
CE mb1_dc1.CPU_A
CE mb1_dc1.CPU_B
CE mb1_dc2.CPU_A
CE mb1_dc2.CPU_B

Does anybody see anything obvious that could be wrong?

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