Inter 'Board' Communication

The satellite processors are on separate boards. How far are they separated from the main board and are they in the same enclosure?

Is the data rate requirement for a sustained, full-duplex between each satellite processor and the main?

LVDS comes to mind as a plausible physical layer.

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Rich Webb     Norfolk, VA

Are you expecting 1MB/s as your total throughput? Or, for each "link"? (i.e., as if star configured)

Do the other processors ever have to talk to each other directly? Or, is everything Master-slave with the Master always the "Main Board"?

Why can't you use the SPI/I2C channels? Can you rethink how you are encoding your data to use lower data rates?

You could use USB host controller on the Main (easy to find MCU's with slave controllers built in).

You could use *SCSI* controllers ("SCSI-1" will give you

5MB/s easily). Not sure if you can find any legacy products (e.g., 5380) for this :-( This also gives you some structure to the data stream (UARTS don't -- you have to impose structure on the "character stream")

Likewise, you can use ethernet and probably strip out the magnetics with some passive trickery (since it is a real short haul and you know *exactly* how many nodes you have).

You can also use an "analog" physical layer (drive a D/AC output to all nodes' A/DC inputs). But, this requires a lot of processing (unless you deal with everything in the time domain and keep your noise floor way down).

Personally, I'd explore the USB route, first. You might be able to spec different processors (if it is early enough in the design stage) for your "slaves" and then just take the hit for an external host controller on the master (there are some MCUs with this ability but nowhere near as many as peripherals).

Less than 50 cm. More something like extensions boards.

Full-Duplex: Yes. Sustained: Depends on the extensions boards. Some have only 115200 Bits/s others have upto 1 MiB/s.

They are close enough. I currently don't think LVDS is needed.

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Optimally for each "link".

Most often only Master/Slave but there should be a possibility for asynchronous replies.

Unfortunately the are all used on the processor. The main processor is currently an OMAP-L138. SPI, UART, I2C, McBSP: Everything is already used. Ethernet is not available (because of pinmultiplexing with McBSP).

That's an idea. The processor has an USB port, I only need a USB hub. Software overhead on the "slave" processors is maybe a bit high.

Noted.

Ethernet is not availble for the current main processor (see above).

I'm early in the design phase and therefore open to anything.

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This could be a potential problem for USB (1.1), then (store-and-forward USB*2* hub??)

But, you can support asynchronous replies within a M-S protocol. I.e., if said protocol causes each slave to be polled regularly then the slave could queue a deferred reply for "next polling time".

Cheat. You "know" what you are talking to. Use that to trim overhead (certain types of error handling) from the protocol.

Decouple the processes to a greater extent. I.e., *don't* expect synchronous messaging. Throw a message to a slave and "move on"; check back later for the reply -- even if the actual "virtual protocol" remains synchronous.

How sensitive is the data? Can you afford to drop any? Can you afford to delay any? Can you afford out-of-order packet handling? etc.

I.e., are you just looking for a NUMA approach to shared memory? Or, something more "abstract"?

1MByte/S is a bit fast for standard async comms. I use the UART ports on MSP430 chips to communicate between ADC boards and a storage system at 115KBaud.

You might try SPI comms. However, clocking at 8MHZ may stress some processors in the slave mode.

Mark Borgerson

For that kind of transfer rates, you will need hardware support for buffering regardless of the transport used. You can certainly stretch UART or SPI or I2C to that speed, however that could result in major inconveniences. The standard solution could be Ethernet or PCIe or some sort of parallel bus with DMA access.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

On the MSP430, I use the UART ports with DMA receive. Since packet lengths are fixed, the DMA setup is fairly simple. The main board prompts for a packet, sets up the DMA for a receive that puts the packet into a queue. The end-of-packet interrupt increments the qeueue pointer and count. If you bumped this up to 1MB/s the DMA might start taking an appreciable part of the CPU bandwidth on a 16MHz CPU. At that data rate, I'd probably switch to an ARM or Cortex at 30 to 60Mhz so I'd have time to do something useful with the data.

SPI is a bit trickier, since it requires a transmit DMA channel to generate the clocks, in addition to the receive DMA channel.

Mark Borgerson

It's uncommon to have speeds about perhaps 921.6 kbaud with RS-232, but there are high-speed RS-485 drivers that work happily with 30+ MBaud. But it's not going to be easy to get a microcontroller's UART to run at the 10 MBaud you need for 1 MB/s - it would have to be external uarts.

s

ve

Perhaps a CPLD ? Depends on the total data rates and usage % and duplex/simplex, but a cpld can do a BUS SPI quite well. It allows SPI on the slaves, in master or slave mode.

-jg

How about a Motorola/Freescale processor with various QUICC co-processors, such as (MC68360,) MPC860, MPC8260 etc. that have at least 4 SCC channels. The main processor overhead is quite low due to the DMA system.

Are the other 4 processors capable of handling 10 Mbit/s speeds through the UART interface ?

While I'm quite sure that the 'main' processor is an OMAP-L138 I'm not sure what the slave processors are. The problem is that I've to think about a possible future, while not making the 'main' board too expensive. But some Cortex-M3 processors with with 80 MHz are a good starting point (somehting between 5$ and 15$).

One idea also had, was using a dual port RAM on every slave board. This allows me to use the A/D-Bus from the 'main' board without investing anything.

I've to add, that I currently investigate the USB idea. The OMAP-L138 has an additional USB 1.1 host controller (The is a possbility that we use the OTG port for something else) and most Luminary Cortex-M3 support Full-Speed (which is enough) and have some additional USB functions included in their ROM. The 'main' board then only needs an USB hub, which seems to be cheaper then a quad UART.

But anyway, thanks everyone for the input.

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Dual-port RAM tends to be expensive -- even if you just opt for a pair of back to back FIFOs. And, it adds explicit synchronization issues that are implicitly handled with a message oriented interface (e.g., USB). Consider it only if you *really* need the bandwidth it will provide.

You also have to be conciously (to some extent) aware of the fact that now you're embracing NUMA and it can have subtle consequences for you (depending on how you use it and the characteristics of your application). Not a "big deal" but not something you can just choose to ignore, either (especially depending on how the DPRAM is implemented)

Remember, you need a "host" *somewhere* in the architecture!

Host (and PHY) is included in the OMAP-L138. OS is Linux. I've already tested it somewhat and the first impressions is ok.

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