DDR2 Skew Constraints

y. This processor has a DDR2 bus speed of 133MHz, which is slow for DDR2 me mories and was wondering if the the DDR2 design constraints, such has Data bus skew etc can be relaxed. The usual requirements are for around 50ps dif ference in track lengths between blocks and 20ps inside the blocks, ie D0 t o D1, I was hopping to get away with 150ps as this makes layout easy and mu ch smaller, with a max track length of around 30mm, min around 10mm. These constraints do not seem to be dependant on bus speed?

y. This processor has a DDR2 bus speed of 133MHz, which is slow for DDR2 me mories and was wondering if the the DDR2 design constraints, such has Data bus skew etc can be relaxed. The usual requirements are for around 50ps dif ference in track lengths between blocks and 20ps inside the blocks, ie D0 t o D1, I was hopping to get away with 150ps as this makes layout easy and mu ch smaller, with a max track length of around 30mm, min around 10mm. These constraints do not seem to be dependant on bus speed?

Sorry for the blank post, hit the wrong key. I have found 133 MHz clocked DDR parts to be completely non-problematic if you just route the signals short, as you suggest (1:3 is may be more tha n I have done but is close). Should work just fine as long as you don't do bad things, like discontinuit ies (cut planes to which the signals are referenced, data groups on different l ayers etc.). But trace lengths are not an issue as long as you put the DDR chips next to the processor and just route reasonably. In a design some years ago I put one series terminator at the processor side and one parallel - to Vtt - at the DDR side; I have seen disconnected parallel term inators on a working board (by accident); never tried to short the serial ones, now these are not that tolerant when accidentally disconnected :D .

Dimiter

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y. This processor has a DDR2 bus speed of 133MHz, which is slow for DDR2 me mories and was wondering if the the DDR2 design constraints, such has Data bus skew etc can be relaxed. The usual requirements are for around 50ps dif ference in track lengths between blocks and 20ps inside the blocks, ie D0 t o D1, I was hopping to get away with 150ps as this makes layout easy and mu ch smaller, with a max track length of around 30mm, min around 10mm. These constraints do not seem to be dependant on bus speed?

ory. This processor has a DDR2 bus speed of 133MHz, which is slow for DDR2 memories and was wondering if the the DDR2 design constraints, such has Dat a bus skew etc can be relaxed. The usual requirements are for around 50ps d ifference in track lengths between blocks and 20ps inside the blocks, ie D0 to D1, I was hopping to get away with 150ps as this makes layout easy and much smaller, with a max track length of around 30mm, min around 10mm. Thes e constraints do not seem to be dependant on bus speed?

Thanks

I confess to being rather lax reducing skew through equalising track lengths. A difference in 20mm should give you 100ps of timing skew depending on the precise microstrip geometry and unless you are at the limit of the memory and processor interface speeds, this level of mismatch shouldn't be a concern.

It is essential to concentrate on minimising reflections and failed designs always seem to exhibit mismatch issues.

If you have a PCB layer stack in mind, there are enough impedance calculators out there for you. Also avoid vias wherever possible!