large FIFO buffer?

Hello all,

I am in the middle of laying out a design for a medical device the reads in data pretty quickly (~20MHz) in bursts, but is limited to a slow serial connection to transfer the data. The solution that comes to my mind is a large FIFO buffer (~100k+) that can take an 8-bit parallel input, but I can't find them anywhere in a reasonable price range. I've looked all over at the common manufactures of logic devices (TI,nationalsemi) and some distributors (digikey,mouser) but can't find much. I hear of hard drives with 512k buffers/caches quite commonly. what am I missing here?

Does anyone know of a model/part# of a pretty high speed, 100k+ fifo buffer?

Thanks in advance for your help.

Best Regards, Adam Kumpf snipped-for-privacy@mit.edu

If it were me I'd also check to see if you ever need to read data in and out simultaneously -- if you can either acquire all of a burst then read it all out entire, or if you can at least pause the readout while a burst is coming in then you'll massively simplify your FIFO design.

As mentioned by the OP, since this is a medical device none of the information I'm giving you should be taken as reliable, it's all made up on the spur of the moment, YMMV, IMHMHUMA, etc.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

FIFOs are fairly unique parts, so don't have the price pressure of more standard devices. SRAMs are dirt cheap, for example. Disk drives don't use large FIFOs for buffers.

I'd use a programmable device (FPGA, probably). Since your requirements are for a significant chunk of memory (an FPGA with that much would be expen$ive), I'd use an external SRAM on a smaller programmable device. 50MHz shouldn't be *too* hard with current devices. The only scary part of the design is "medical device". ;-)

--
  Keith

haha.. no worries about legal issues.. just trying to get a quick prototype up and running for proof of concept. Everything will be thoroughly verified before any production level circuitry is decided upon. :)

Thanks for all of your help. The SRAM decision only slightly complicated the design, but reduces the price drastically(by a factor of 10 or more!)... just what I was looking for! :)

Thanks again.

Best Regards, Adam Kumpf

reads

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drives

I agree that a "roll your own" FIFO is the way to go, if production cost is your major concern. You should be able to fit this into a CPLD with

128 macrocells, unless you have other requirements that make the control logic particularly complex. This will remove the need for powerup programming of an FPGA. OTOH, using an FPGA that is programmed by your processor allows you to easily modify the code in the field, assuming your product will be designed for software field upgrades anyway.

I know Xilinx has proven code available for FIFOs and I think Altera does as well, although these probably assume the RAM is internal and dual-ported. You can check at opencores.org to see how their FIFO fits your app but you may not like the licensing issues.

50 MHz should be no problem at all for either a CPLD or FPGA of the current generation. I've been doing 133 MHz FIFOs inside FPGAs for several years now.

Ooo-ooo-oo . . . (involuntary shudder), just the thought of the liability makes my toes curl. ;-)

On that note, please apply all the usual disclaimers about me not being liable for *anything* as a result of your use of my completely uninformed and most likely incorrect suggestions. (want to put a smiley here but I'm too afraid of the lawyers)

--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . .  VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada  . . . . . . . . . . . http://www.marmot-eng.com

Averlogic have nice big fast FiFo's

and the price is pretty good

Greezt,

Markus