I2C bus needs capacitance?

a . s

The 5V side, longest trace from the level shifting MOSFET to device is appr ox. 6cm. The 3.3V (master) side is mostly a ribbon cable, 50cm.

Unfortunately, the master is most definitely not 5V tolerant. I previously tried this circuit using only 3.3V pullups, which is safe, as the slaves o nly ever pull the lines low...but communication was unreliable. The master is a micro, but I do not have control over it. It has been proven to work reliably in other situations.

I lifted a couple pads trying to cram in a couple TO-92 onto that little SO Tting pad. Now I'll have to rig up something between the ribbon cable and this board to test.

I run the I2C at only 100kHz...hoping to avoid these kind of troubles.

I very much appreciate everybody's input. Things are making more sense now , and you have given me much food for thought.

"rock solid" through a 10k resistor:

You are right, but as it seems only partially.

I've just tried to spice-model the circuit (with the likely drive signals and parasitics) and the timings (with no load at the slave side) didn't initially look too fast - tens of nanoseconds but not single nanoseconds. The fast negative pulse effect was clearly visible in the simulation. Although it can't really be all due to reflection, it did get rather worse when I added 10 nanoseconds of transmission line (terminated to 47 pF at the end) to the model.

In any case, something is still being coupled into the gate (I suppose through the G-D capacitance) and this plays a very big role. The pulse problem disappears practically entirely when the gate resistor is changed from 10 kOhm to 10 Ohm. Then the FET will just "conduct", as you described.

Dimitrij

Funny, I saw the datasheet but didn't spot the gate resistor.

Either way, pulling the source low will pull the gate capacitively with it, which is anything, will delay the turn-on.

What it does do, however, is introduce more capacitive coupling between the source and the drain, which I believe is the issue.

--
Mike Perkins 
Video Solutions Ltd 
www.videosolutions.ltd.uk

Is this without a 5V load resistor?

The OP says there is just 6cm of track on the 5V side, so a sub-ns reflection which I feel we can discount.

Can you try with a 5-10k load to 5V?

--
Mike Perkins 
Video Solutions Ltd 
www.videosolutions.ltd.uk

If it's actually "I2C", it doesn't need level shifting.

The standard /is defined by/ 5V signal levels.

I2C devices regularly operate on lower VDD, usually having "5V-tolerant" pins to accommodate the higher signal level.

If it's not I2C, but SMBus or something like that, then it should still be good enough to use a pull-up to somewhat more than 3.0V (perhaps 3.3 or

3.6V).

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:

The I2C master is 3.3V while all the slaves are 5V devices. This works fine, except on the newest board. Only one of the (3 in this case) slaves respond. Scoping the wave-forms and comparing with another board with the same circuit (different PCB layout, however) shows they are identical...until I noticed something odd:

With the scope probes attached the new board works fine! Testing with a bare finger instead of probe yields about an 80% success rate. The probe/finger must be at the node marked 'Master SDA', nowhere else has any effect.

I'm only running at 100kHz. Can anybody enlighten me to what may be going on? Do I really need to hang a cap off a serial data line??

Feels like I'm missing something obvious here...

Even if not tolerant, they often allow a modest current to be drawn through the I/O protection diode. That then allows a 'high' signal of nearly 4V from a pullup resistor to 5V.

I have never had to use level translators and have found that 3.3V I2C can still provide a reliable logic '1' for 5V devices.

--
Mike Perkins 
Video Solutions Ltd 
www.videosolutions.ltd.uk

Thank you everybody who weighed in, my problem has been solved.

Using MOSFETs without an integrated 10K gate resistor immediately and defin itively cured the issue. The scoped traces now look nearly perfect. The ' mush' at the top is gone, as is the 'bounce' on the negative edge. The sys tem has been communicating with all devices without a single hiccup all mor ning.

e

Thanks, Tim. I'm sure you are correct.

In this particular case I have no control of, and little knowledge about th e master, and am constrained by other things out of my control. I was told in no uncertain terms that the master must not see 5V. Clearly the master doesn't conform exactly to I2C standards, and is more like SMBus.

You do have me reconsidering, however, our assumption that when we tried th is years ago at 3.3V everywhere that that was the cause of our sometimes fa iled communications.

Thanks again, your input is much appreciated.

Thanks, Mike. I will definitely consider it the next time I have to do something like this.

In case anybody was interested in the final scope traces:

This is with 5K pullups. I will using stronger pullups moving forward, in order to stiffen up that rising edge.

Ok, without the transmission line, there is no ringing after the spike.

The model was already including that (10k pull-up to 5V), otherwise the slave-side signal would never rise above 3.3 V in the first place.

The slave itself was modeled as 47 pF + 100 Ohm to ground, at the far end of a 10 ns 70 Ohm transmission line. But it hardly matters - when it's removed, the falling part of the negative spike remains the same, only the ringing after that disappears.

On 07.10.2016 20:27, Dimitrij Klingbeil wrote:

P.S. Here's the LTSpice model I used

--------------------------

Version 4 SHEET 1 1040 984 WIRE 272 -224 -416 -224 WIRE 272 -176 272 -224 WIRE -416 -128 -416 -224 WIRE 752 -96 672 -96 WIRE 272 -64 272 -96 WIRE 272 -64 112 -64 WIRE 384 -64 272 -64 WIRE 752 -64 752 -96 WIRE 112 -32 112 -64 WIRE -416 0 -416 -48 WIRE 272 16 272 -64 WIRE 448 16 272 16 WIRE 752 48 752 0 WIRE 112 64 112 32 WIRE 448 64 448 16 WIRE 512 64 448 64 WIRE 672 64 672 -96 WIRE 672 64 608 64 WIRE 512 96 448 96 WIRE 672 96 608 96 WIRE 272 128 272 16 WIRE 448 128 448 96 WIRE 672 160 672 96 WIRE 752 160 752 128 WIRE 752 160 672 160 WIRE -64 208 -416 208 WIRE 112 208 112 128 WIRE 112 208 16 208 WIRE 224 208 112 208 WIRE 752 208 752 160 WIRE -416 256 -416 208 WIRE 272 304 272 224 WIRE 384 304 272 304 WIRE -416 368 -416 336 WIRE 272 448 272 304 WIRE 320 448 272 448 WIRE 512 448 400 448 WIRE 512 480 512 448 WIRE 16 496 -16 496 WIRE 112 496 96 496 WIRE -16 528 -16 496 WIRE 512 592 512 560 WIRE -256 608 -416 608 WIRE -64 608 -176 608 WIRE 112 608 112 496 WIRE 160 608 112 608 WIRE 272 608 272 448 WIRE 272 608 256 608 WIRE -416 624 -416 608 WIRE 160 640 112 640 WIRE 336 640 256 640 WIRE 336 688 336 640 WIRE -416 736 -416 704 WIRE -16 736 -16 624 WIRE 112 736 112 640 WIRE 112 736 -16 736 WIRE -16 768 -16 736 FLAG -416 368 0 FLAG -16 768 0 FLAG -416 0 0 FLAG 448 128 0 FLAG 336 688 0 FLAG -416 736 0 FLAG 752 208 0 FLAG 384 -64 Output FLAG 384 304 Input FLAG 512 592 0 SYMBOL nmos 224 128 R0 SYMATTR InstName M1 SYMATTR Value 2N7002 SYMBOL res 32 192 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 10k SYMBOL zener 128 128 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D1 SYMATTR Value BZX84C12L SYMATTR Description Diode SYMATTR Type diode SYMBOL zener 128 -32 M0 SYMATTR InstName D2 SYMATTR Value BZX84C12L SYMATTR Description Diode SYMATTR Type diode SYMBOL voltage -416 240 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 3.3 SYMBOL nmos -64 528 R0 SYMATTR InstName M2 SYMATTR Value 2N7002 SYMBOL voltage -416 608 R0 WINDOW 3 28 87 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 24 124 Left 2 SYMATTR Value PULSE(0 3.3 10u 2n 2n 10u 30u) SYMATTR InstName V2 SYMBOL res 304 464 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL res 256 -192 R0 SYMATTR InstName R3 SYMATTR Value 10k SYMBOL voltage -416 -144 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value 5 SYMBOL tline 560 80 R0 WINDOW 0 2 -19 Bottom 2 WINDOW 3 3 20 Top 2 SYMATTR InstName T2 SYMATTR Value Td=1n Z0=70 SYMBOL res 736 32 R0 SYMATTR InstName R4 SYMATTR Value 100 SYMBOL cap 736 -64 R0 SYMATTR InstName C2 SYMATTR Value 47p SYMBOL res -160 592 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 15 SYMBOL res 112 480 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 10 SYMBOL tline 208 624 R0 WINDOW 0 2 -19 Bottom 2 WINDOW 3 3 20 Top 2 SYMATTR InstName T1 SYMATTR Value Td=5n Z0=100 SYMBOL voltage 512 464 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V4 SYMATTR Value 3.3 TEXT -424 832 Left 2 !.tran 200u TEXT -416 432 Left 2 ;Fast open-drain driver with Zout = 10 Ohm \n(microcontroller output) TEXT 152 528 Left 2 ;Ribbon \ncable TEXT -160 -80 Left 2 ;Transient suppressors \n(for parasitic C_gd) TEXT -88 272 Left 2 ;Gate resistor TEXT 520 -16 Left 2 ;Output\nwiring TEXT 672 -144 Left 2 ;Dummy load

Interesting how the gate is pulled low through Cgs and the Output initially through Cds etc.

The Output tries to recover towards 5V before the gate voltage also rises and conduction starts.

But then why would anyone put 10k in series with the gate?

--
Mike Perkins 
Video Solutions Ltd 
www.videosolutions.ltd.uk

Well, as the OP has now found out, it was not such a good idea.

The reason is, that is was a relay driver transistor. An application specific part designed for switching relays and electro-mechanical actuators that are inductive in nature.

With the integrated gate resistor and gate-drain voltage suppressor it automatically provides inherent limiting to both V_ds and dV_ds/dt. When a relay is switched off, initially the gate voltage only starts falling slowly (thanks to R_g) and the rising V_ds (from the relay Back-EMF) couples into the gate via C_gd, which acts as a (risetime dependent) negative feedback and further keeps dV/dt down. As soon as V_dg reaches the conduction level of the voltage suppressor, it also couples a DC offset into the gate, which biases the FET to linear mode and clamps the drain voltage, preventing it from rising any higher. Together these effects make relay switching a rather painless operation from the EMC point of view (since neither V nor dV/dt is uncontrolled).

The only problem is that this transistor is of little use for anything else besides driving relays and similarly slow items :)

If I2C is open collector/drain and 5 volt circuits work reliably with a

3.3 volt pullup, can't you just eliminate both the 5 volt pullup and the level converter? Or is that what Tim is saying?

Even if the 5 volt pullup is beyond your control, can't you connect the data/clock lines to the 3.3 volt rail with Schottky diodes, protecting the 3.3 volt devices? You can get Schottky diodes in 0603 compatible packages to replace the 3.3 volt pullups. Then you only have to jumper around the FETs and you are done.

--

Rick C

I believe that is what Tim is saying. The OP said this lead to unreliable communications, though without more information we don't know why.

My perspective is that I2C was never intended to cross lengths of ribbon cable with origins of a single board to reduce interconnect to control items like audio and tuner settings.

To be fair to the OP the only reason why the circuit failed was he used a relay driver to accomplish the level translation. The principle of using a FET in this manner is quite common though not one with a gate resistor.

The other thing we don't know what happens when the OP got a data or acknowledge fail. The usual behaviour is to retry a number of times before signalling failure.

I don't feel a 5V pullup with Schottky diodes serves any real purpose apart from synthesising a ~3.6V pullup resistor albeit with a faster slew.

--
Mike Perkins 
Video Solutions Ltd 
www.videosolutions.ltd.uk

Definitely. We once had a problem with I2C on an interboard connector, with loads on both sides of the connector. Even a .5K pullup was iffy (definitely wouldn't have shipped that way). An I2C accelerator solved the problem. They're way too expensive for an production I'd do now but if I'm in a position where I2C has to go through a connector, I place a footprint for one, just in case.

I2C Accelerator example:

RED FLAG

If you had mentioned a ribbon cable in your OP...

I2C was never intended to leave a PCB, and trying to do so is iffy at best!

On the rare occasions I'm forced to do it anyway, I try my best to filter RFI and clamp transients. This usually involves ferrite beads and extra bus capacitance (C || R+C to bypass /and/ dampen it), and clamp diodes (BAT54S or 5V zener).

Ideally, it would involve more series resistance too (especially where ESD is expected), but the permissible amount is very limited, due to the open-drain signaling.

Likewise, the amount of filtering permissible in the low MHz range is limited (without violating cable length and transition timing constraints). What separates something like RS-232 from I2C, is not just the signal level (nominal +/-15V vs. 5V), but the noise-immune design of the receiver (multiple sample points per symbol, voting resolves noise). You can always push RS-232 to a lower baud rate and get better reliability, but the same needn't be true of I2C or SPI (which are synchronous).

And you can't do common-mode filtering, because the signals are not differential.

Where the signals reach a connector, ideally, the connector is shielded, and the shield is tied into the board ground plane. If multi-conductor (un-shielded/screened) must be used, then reserve half the wires for grounds, interleaving them between signals. (A 0.05" pitch ribbon cable would use a two-row IDC header, where one complete row is grounded. Super simple!)

This basic filtering and grounding makes the link resistant to a few V/m of RFI (>30MHz). For short runs without ground loops (e.g., an HMI board a short distance from the main board), it's not susceptible to EMI (the length is too short to have significant voltage drop