1. Home
  2. Electronics Design
  3. FPGA sensitivities
  4. Page 2

FPGA sensitivities

Fixed both problems.

Jitter: replaced the 1.8V Vccaux switcher with a linear regulator.

Temperature-dependant crashing: I found an oscillation on the Zynq 1v core power supply, about 100 mV p-p and 80 KHz. Putting a lot more capacitance at the switcher output kills that and makes the crash go away. The regulator design followed a chart in the LTM8078 data sheet. A Spice sim with the original values looks stable, no oscillation and a clean load-step recovery.

There are other indications that ADI's Spice model of the LTM8078 is less than perfect. I think ADI is struggling to add a lot of new parts to the LT Spice libraries. Mike E in an interview suggested that rushing them out was compromising quality. Then he quit.

Glad I fixed this this way. Guys were snooping the AXIbus and Linux at great expense and no progress.

Reply to
John Larkin
Loading thread data ...

mandag den 5. oktober 2020 kl. 22.06.28 UTC+2 skrev John Larkin:

I believe the mixed mode clock manger and pll in the PL is powered from Vccaux

Reply to
Lasse Langwadt Christensen

I did a static sensitivity test on the critical-path FPGA. It showed essentially zero through-chip delay vs Vccaux. It was super sensitive to core voltage. But the +1 core supply was LDO'ed from the noisy 1.8, so maybe some noise sneaked through there.

I'm going to rip out some switchers and use a chain of LDOs to make the various supplies for the critical XC7A15 FPGA. The Zynq is not in the picoseconds-time-critical path.

+5 ldo to 3.3 for i/o banks 3.3 ldo to 2.5 for the bank that does LVDS 2.5 ldo to 1.8 for aux 1.8 ldo to 1.0 for core

in one long string.

We're using ST1L08 regs, super low dropout, good filtering, small and cheap.

Reply to
John Larkin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.