I'm using one of these little PCB mount impedance matching transformers "backwards" in my junk box cap charger, and am trying to select a value of DC blocking capacitor to put in front of it. I think I've been trying to use a value of a few nanofarads in the prototype and it's not right, there is a lot of ringing and nastyness coming out of the secondary.
Here is the datasheet on the surplus tranny:
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I'm using the output secondary of the "OUTPUT" type that has a 0.3 ohm DC resistance on it as the primary, and the 42 ohm resistance primary as the secondary.
I think based on the core size that it should have enough bandwidth at 20kHz to work OK, but basically I need approximate figures on the secondary inductance, leakage inductance, and parasitic capacitance at that freq. to f*ck with a value in LTSP...er, carefully solve the equations and select a coupling capacitor.
I was surprised that the China Special LM386s I have seem to have a great deal of bandwidth left even outputting 20-30kHz; so long as the input divider is selected such that the output isn't slamming the rails the square wave looks to have very sharp edges when the gain pins aren't bypassed, and closed loop gain = 20.
For an AC input coupling capacitor you only need to worry about the transformed load impedance at high frequencies, and the magnetizing inductance at your desired low-frequency cutoff. The DC resistances likely won't matter. If necessary, you can estimate the magnetizing inductance from the low-frequency spec information.
It's feeding a bridge voltage doubler and 350 volt photoflash cap floating on the secondary side, so how would I figure a ballpark transformed load impedance on that?
For the magnetizing inductance, all I have to go on are the specs as given in those links, and the fact that it appears to be an "E core" geometry with a weight of about ten grams.
You're probably working at a high enough frequency to ignore the magnetizing inductance. Transform the load impedance by the square of the turns-ratio. A big enough coupling cap will insure that it won't be part of the scene.
20kHz is too high to speak meaningfully of inductance and leakage. Either you're in the range of parasitic capacitance already, or the "switching" harmonics definitely will be.
They work pretty well in the kHz. Hope you don't mind a little whine. ;-)
Otherwise, snag an inverter transformer off Digikey. 5V to 120V, single watt transformers are off-the-shelf -- if pricey ($5, but hey, you're paying for agency-approved Reinforced insulation). Run 'em at 100kHz or more, easily achieved with, say, a 2N4401 oscillator, or preferably something fancier (UC3843 or better).
I'm using one of these little PCB mount impedance matching transformers "backwards" in my junk box cap charger, and am trying to select a value of DC blocking capacitor to put in front of it. I think I've been trying to use a value of a few nanofarads in the prototype and it's not right, there is a lot of ringing and nastyness coming out of the secondary.
Here is the datasheet on the surplus tranny:
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formatting link
I'm using the output secondary of the "OUTPUT" type that has a 0.3 ohm DC resistance on it as the primary, and the 42 ohm resistance primary as the secondary.
I think based on the core size that it should have enough bandwidth at 20kHz to work OK, but basically I need approximate figures on the secondary inductance, leakage inductance, and parasitic capacitance at that freq. to f*ck with a value in LTSP...er, carefully solve the equations and select a coupling capacitor.
I was surprised that the China Special LM386s I have seem to have a great deal of bandwidth left even outputting 20-30kHz; so long as the input divider is selected such that the output isn't slamming the rails the square wave looks to have very sharp edges when the gain pins aren't bypassed, and closed loop gain =
--
Thanks. So is there a general rule then for selecting an
appropriate coupling cap? JL recommended in the 20uF range, I
didn't realize it would need to be so large.
I have the tranny on hand. I'm using a C4093 gatable square wave
oscillator type arrangement so I can control the thing from a uC
output, and then feeding that into an LM386 driving the
transformer for power gain.
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More may be desirable, e.g. for electrolytics, because of their relatively high ESR and low ripple ratings.
That... doesn't sound like something that should be cap-coupled... or done at all.
Ideally, for starting and stopping an inverter, you want the idle at zero (assuming bipolar power supplies), the starting pulse is timed for about a quarter wave (actual ideal timing varies because of ESR), then the square wave continues as normal.
Think about the flux in the transformer during startup, and you should see why this is so.
If you're using LM386 as a binary driver, then its output is either near-Vcc or near-Vee, never inbetween (except during the rather gratuitous "switching" edges). This violates the first consideration, that idle should be near zero.
If you're just gating the clock on and off asynchronously, then the first and last pulses will be random length. Which puts a random amount of initial flux into the core, between +/- Vcc / (4*Fsw). This might not be a problem (a transformer designed for some volts at 100Hz will still be far from saturation), but it's inelegant.
The excess flux also supplies an impulse to the LC resonant circuit formed with the coupling capacitor and primary inductance (that's the winding you're driving, to be clear :) ). The ringing transient can draw more peak current than the circuit is expecting.
A synchronous clock gate could be made by starting with 2*Fsw, dividing it in half with a T-strapped D f/f, and using a few gates to generate the quadrature signal (CLK XOR Fsw = Fquadrature, or use another D f/f and a NOT to delay Fsw by !CLK). The divided signal is simply Fsw. Use the delayed signal to gate the DAC.
Now what I mean by gated DAC is, you need a signal output that's normally
0, then becomes (Fsw * 2 - 1) (i.e., +/- 1) when gated on. A tristate DAC. The analog level need not be very precise if you're overdriving the '386, so it might simply consist of a few gates and resistors, but it is basically intended to convert from digital to analog, so calling it a DAC is true.
This circuit does the job, with some dead time inbetween for good measure. You don't need that, of course, but you could use the rest of the thing for PWM regulation.
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In normal use of such a chip, PWM changes slowly enough that the startup transient averages out. This thing being hard wired for operation, won't do quite as well. It probably should have a coupling cap, too, though the class C output stage allows some leeway.
Ok, but I'm not sure how to figure what the transformed impedance of the secondary is. For the majority of the cycle the impedance "looking in" to the bridge and smoothing cap is infinite, yeah? Conduction is only happening on a small part of the cycle.
But the while the LM386's inputs are ground referenced, the output automatically biases up to 1/2 the supply voltage (I'm using a single positive supply.) And I need to keep the DC bias out of the core.
Well, don't just throw up your hands, look at what's happening on that small part of the cycle!
You can use some approximations to figure out the duty cycle, as if it were square pulses of current (and assuming sinusoidal waveform). This works pretty well for a mains rectifier.
Or if it's properly square after all, the load will be constant, only dropping during switching. Though switching will be charging that parasitic capacitance, so the amplifier will always be working.
With a low impedance square wave drive, you'll actually see a reasonable square on the primary and a lumpy one with overshoot on the secondary. The ringing is due to leakage inductance resonating with the secondary's parasitic capacitance. If the load is light, the peaks may well deliver most of the load current. Which will give you terrible regulation at light loads, of course.
Or you can use a power argument. If you've got Po = Vo * Idc output, you need _at least_ Iinv = Po / Vinv and likely 2-4 times this, to account for rectifier pulses and transformer reactances.
So the equivalent, average impedance seen by the inverter is Vinv / Iinv.
This also works for more subtle aspects of inverter design, such as, the ideal snubber impedance is on the order of Vo(pp) / Io(pk).
Well... the datasheet doesn't actually define how much that offset is. So, you're kind of screwed.
Actually, the datasheet tells about crap-all of anything. No bias tolerance, no offset tolerance, no gain or ratio tolerance...
The equivalent schematic shows right around half (and is probably an okay ratio), at least.
What you can do for this case is use a faked floating ground: make a capacitor divider between VCC and GND. One end of the primary goes to the inverter, the other end goes to the tap on the C divider.
If the supplies are well bypassed (Cbyp >> Cdiv), the (Thevenin) equivalent capacitance at the divider node is 2*Cdiv.
Place the divider near the LM386, since it serves as local bypass, too.
You still need the "return to zero" waveform though. Perhaps taking Fsw and its NOT, and gating both (using AND or NOR) to the + and - inputs through resistor dividers? (If the logic is 74HC at 5V, then a 10k + 1k divider gives 0.45 or 0V output, which will be enough to saturate the LM386 in either direction, for supplies up to 18V.)
Thanks for the tips! Ideas for the next iteration - it seems to be working OK just putting the DC blocking capacitor of a few dozen uF after the 386 output and feeding the transformer primary (secondary) from that.
There's no continual load on the secondary, it just charges up a big capacitor to be dumped thru a flash tube.
As it is right now with the doubler on the secondary and using two 2.2uF 250 volt electrolytic caps in the doubler the circuit charges up a 47uF photoflash cap in a couple seconds.
I was hoping to hear whine, but I'm headed into middle age and at 20kHz I don't hear a thing. :(
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