Finally got the OS running on the RP2350 emulator

Oct 28, 2026 Last reply: 20 hours ago 4 Replies
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It took forever, but I finally got my target operating system to fully boot on the Pico 2 emulator. Seeing the shell start up after all that setup was a huge relief. It's amazing to see a full 64-bit system just running on a chip that small.



I hit a major wall with memory right at the start. The standard allocation routine for the OS was trying to reserve way too much space, wich basially killed the whole thing immediatly. The fix was as simple as changing the block size, but it took me days to find that exact line of code that needed adjusting to fit the hardware limitations.



Now I can run basic commands and utilities in the console, and they execute without any stalls or crashes. It’s a huge win for running complex software on these kinds of constrained platforms. Just a cool experiment to wrap up the week.


I ran into a bit of a headache myself when getting the xv6 kernel to recognize the hardware properly. While memory space was tight for me too, my main stumbling block was timing related to the peripheral registers. If the interrupt controller wasn't mapped and initialized at the exact right millisecond during the boot sequence, the whole thing just locked up immediately, even if the RAM allocation was perfect.

I was using a slightly older simulation enviroment, maybe QEMU, and I had to manually adjust the setup file to ensure that the specific clock speed for the GPIO was being passed correctly into the kernel from the loader. It seemed like a tiny detail, but without that correct frequency, the UART wouldn't initialize, and I couldn't even see the boot message appear in the console. It was frustrating trying to trace why the output wasn't popping up.

After adjusting that clock parameter in the config file, the boot sequence finally hit the expected checkpoint. It wasn't about having more space; it was about the sequence of communication between the simulator and the chip's I/O. Once that bit clicked, everthing else started behaving like it should.

My setup ran into a completly different roadblock when I was trying to get the boot sequence to run efficiently on the Pico 2. I got it running, but the initialization felt like it was dragging forever, especially when trying to use the emulated clock cycles. It wasn't the allocation that killed it; it was the sheer number of unnecessary loops running during the startup phase. I spent a good portion of an afternoon looking at the initial stack setup code. Turns out, the default logging routine was doing far too much work before the kernel even switched to protected mode. It was trying to dump status information to what was essentially a phantom serial port, which just ate up valuable time that the emulator needed to properly spin up the RISC-V core.

I managed to bypass most of that logging immediately, just adding a simple print statement for major milestones instead. The boot time dropped significantly, which felt like a huge relief once you realize how much overhead the boilerplate code is generating just to say 'hello' before the main kernel loop even begins.

I found the debugger setup itself was way more of a pain than the actual kernel code. Getting the RISC-V register states to map correctly in my emulator was hell. Once it was actually running, though, I noticed the frame rate was awful. Even with a clean boot, the emulator's overhead was slowing things down dramatically. I spent a solid couple of hours just trying to get the console output to scroll without stuttering. It wasn't about the kernel itself; it was purely the simulation environment not being fast enough for smooth operation.

The biggest performance drag for me wasn't the register mapping, it was the branch prediction accuracy on that core. When you run xv6, the compiler generates a lot of heavy 'if/then' logic that the hardware really struggles with. I measured my average CPI (cycles per instruction) dropping to 3.8 when running simple shell commands, which is far above what the documentation suggests for a single-cycle core.

I found that optimizing the memory layout to keep critical kernel code within the first 256KB of cache significantly reduced the overhead. Otherwise, you spend too much time waiting for RAM hits, and the whole system just bogs down. It really comes down to making the core code as tight as possible.

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