How do I know if my trace routing is good enough before I order this board?

Traces running under the body of the chip are totally normal. The underside of a QFP package is plastic with no exposed metal there, so nothing shorts. The only place you have to be careful is keeping those traces away from the center pad region itself, since that connects to the ground pour. If your routing clears that island, you're fine. The exposed pad tied down with a handful of vias is exactly what you should be doing. More vias is better than fewer, but for a flight computer running at modest speeds even four or five is plenty. I'd worry more about the paste stencil on that pad, if you get solder squeeze-out it can lift the chip off the surface. Ask your fab for a thinned paste layer on that footprint or a segmented one.

On the caps, close-ish is honestly good enought for an STM32. These chips are pretty forgiving and it'll run fine with caps a few mm out. But since you said revisions cost you money, I'd shuffle the placement anyway. The trick that usally works is moving the connector first, let it push the caps, then reroute the caps to thier pins as short and direct as you can. One cap per power pin, placed before you route anything else. If you find one you just can't get close, put the bulk cap nearby and route it first.

Before ordering, my checklist is: run the design rule check with real clearances, print the copper layout at 1:1 on paper and physically place your connectors and any headers on it to check fit, and re-verify every footprint pin numbering against the datasheet. Check that you can actually reach the programming pins and the boot pin after assembly, because you will need to reflash it. And check the accel range on your sensor against what your rockets pull, if you fly something punchy that little chip might saturate and give you garbage altitude data.

I agree that maximizing current delivery is more critical than micro-optimization of cap placement. I once had a flight controller that blew beacuse I underestimated the current needed for the peripheral components. You absolutely have to calculate the maximum expected current draw and size your power traces based on that. For a device like this pulling around 2.5 Amps, I always sized my main power lines to at least 20 mils wide to ensure zero voltage drop across the board. It is much safer to have an over-engineered trace than to worry about a slight cap shift.

I totally agree with the point about sizing the power traces based on the expected current draw. It is so easy to just use the standard values and forget to account for peak loads. When I was putting togehter my last flight board, I realized my main power plane was a bit narrow. I had to double its width to prevent any voltage drop during startup, and it made a huge difference in the stability of the telemetry signals.

It's better to over-engineer the power lines than to worry about the layout being perfect everywhere else. Make sure you double check your power input stages, expecially where you switch from the main rail to the peripheral voltage regulators.

I don't think just widening the main power plane is the biggest fix for stability, like the last poster suggested. They talked about resistance and doubling the width, but that mainly handles DC voltage drop. For an STM32, especially with all those high-speed I/O signals, the biggest issue is actually the inductance in the loop. The distance between the capacitor and the power pin matters way more than the thickness of the trace itself. A thick plane helps, but if the immediate power loop is big, you're still going to see some ringing or voltage spikes that a wider trace alone won't fix.

I totally get the inductance point about the power loops being way more important than just the width of the traces. My situation is a little diffrent since I'm doing a smaller project for home automation instead of flying things around, but I'm running into the same physical space issues. I've been struggling with how to get the signal ground away from the main power plane without messing up the decoupling placement. It feels like for every millimeter I move the power supply traces, I lose critical space for the filtering components. I'm worried that if I make the ground pour too big to keep things clean, I might mess up the routing for the digital signals.

Update: relief on the routing front, turns out traces under a QFP are standard practice and just need clearance around that center pad, which is what I figured but second guessed. Checked my current draw numbers like the power sizing posts suggested and they look okay. Still stuck on the caps sitting a bit far from the pins though. How far is too far before it actualy causes problems?